Congestion Driven Placement for VLSI Standard Cell Design

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Congestion Driven Placement for VLSI Standard
Cell Design
Shawki Areibi and Zhen Yang School of
Engineering, University of Guelph, Ontario,
Canada December 2003 (sareibi_at_uoguelph.ca,
zyang_at_uoguelph.ca)
ICM 2003, Cairo
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Outline
Introduction
Background
Motivation
Congestion Optimization
Experimental Results
Summary Conclusions
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Introduction

• The interconnect has become a critical determiner
  of circuit performance in the deep sub-micron
  regime.
• Circuit placement is starting to play an
  important role in todays high performance chip
  designs.
• In addition to wire length optimization, the
  issue of reducing excessive congestion in local
  regions such that the router can finish the
  routing successfully is becoming another
  important problem.

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VLSI Design
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Layout Style
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Standard Cell Layout Style
Feedthrough

• Feature
• Row based layout
• Standard cells
• Routing channel

Standard cell
I/O Pads
Routing Channel

• Advantages
• High productivity
• More efficient space
• Well-suited for automated design

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Circuit Layout - Partitioning
Task
Partition circuit into several sub-circuits.
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Circuit Layout - Placement

• Minimize the total estimated wire length of all
  the nets.
• Minimize the interconnect congestion.

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Circuit Layout Global Routing
Objectives
Minimize the total wire length and critical path
delay.
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Circuit Layout
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Why Is Placement Important?

• The circuit delay, power dissipation and area are
  dominated by the interconnections.

- Circuit Placement becomes very critical in
todays high performance VLSI design.

• The first phase in the VLSI design that
  determines the physical layout of a chip.

- The quality of the attainable routing is
highly determined by the placement.
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Placement Techniques
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Traditional Placement Approach
Circuit Generated From Logical Description
Initial (global) Placement by Constructive
Algorithms

• Produce a good initial placement in reasonable
  time

Improve (detailed) Placement by Iterative
Algorithms

• Produce a good final placement

Valid Coordinates for each cell
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Multi-Level Clustering

• Bottom-up procedure (clustering)
• 2. Top-down procedure (de-clustering)

initial placement iterative improvement
a simple interchange heuristic
a high quality solution
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Traditional Methods Drawbacks

• May lead to routing detours around the regions (
  i.e. larger routed wire length).
• May create an unroutable placement( i.e leads to
  replacement and repartitioning).
• Congestion reduction in placement stage
  
  would be more effective.

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Congestion
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Congestion Reduction Techniques
Congestion Reduction
Integrated Technique
Post-processing Technique
Simulated Annealing
Quadratic Placment
Congestion Reduction During Placment
Partitioning Based Placement
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Congestion Optimization
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Routing Estimation

• Bounding Box Routing Estimation.

For each yellow bin, the Horizontal Routing
Demand of net K is1/3
Total Horizontal Routing Demand of net K 2
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Congestion Cost Function
Wire length
Overflow
Total Bounding Box Based Wire length 4
Horizontal Routing Demand 2 Vertical Routing
Demand 2
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Identifying Congested Regions

• A global bin is congested if one of its four
  global edges is congested.
• A maximum number of congested bins in one
  congested region is set to prevent forming too
  large congested regions.

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Congested Region Expansion

• For a single congested region, the larger the
  expansion area is, the better the optimization
  result can be obtained.
• However, the expansions of multiple congested
  regions may lead to new congested regions.

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Test Circuits
Circuit cells Pads Nets Pins Rows
Fract 125 24 147 876 6
Prim1 752 81 904 5526 16
Struct 1888 64 1920 5471 21
Ind1 2271 814 2478 8513 16
Prim2 2907 107 3029 18407 28
Bio 6417 97 5742 26947 46
Ind2 12142 495 13419 125555 72
Avq.s 21854 64 22124 82601 80
Avq.l 25114 64 25384 82751 86
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Experimental Results

• Test Circuit Statistics (for flat approach)

Circuit cells Nets Grids c/bin V/H Cap
Fract 125 147 6x9 2.3 6/6
Prim1 752 904 16x21 2.2 11/10
Struct 1888 1920 21x32 2.8 8/7
Ind1 2271 2478 15x54 2.8 19/7
Prim2 2907 3029 28x49 2.1 16/13
Bio 6417 5742 46x60 2.3 11/10
Ind2 12142 13419 72x76 2.2 17/20
Ind3 15059 21940 54x111 2.5 27/20
Avq.s 21854 22124 80x114 2.4 12/10
Avq.l 25114 25384 86x120 2.2 12/10
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Congestion Reduction (at flat level)
Average Congestion imp 51
Average Wire length Increase 3
Average CPU Time Increase 30
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Congestion Reduction (at level-3)
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Results Analysis

• Incorporating a post processing technique into
  the hierarchical placement may not be an
  effective way to reduce the congestion due to the
  interplay between the wire length placement
  algorithm and congestion reduction technique.
• The wire length minimization should be performed
  on clustering levels, while the congestion
  optimization should be only turned on at the flat
  level.

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Congestion Reduction (after hierarchy)
Average Congestion imp37
Average Wire length Increase 3
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Conclusions and Summary

• A post-processing congestion reduction technique
  is implemented and incorporated into the flat and
  hierarchical placement.
• A post-processing technique can reduce the
  congestion of flat placement largely by 51 on
  average with a slight increase of wire length.
• For hierarchical congestion-driven placement, it
  seems to be more beneficial to incorporate the
  congestion reduction phase at the flat level
  rather than within the levels of hierarchy.
• The congestion improvement achieved by performing
  congestion optimization at the flat level is 37
  on average.

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Thank You !
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Congestion Driven Placement
(channel capacities2) Unroutable Layout
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