OUTLINE

1
Lecture 19

• OUTLINE
• The MOSFET
• Structure and operation
• Qualitative theory of operation
• Field-effect mobility
• Body bias effect
• Reading Pierret 17.1, 18.3.4 Hu 6.1-6.5

2
Invention of the Field-Effect Transistor
O. Heil, British Patent 439,457 (1935)
In 1935, a British patent was issued to Oskar
Heil. A working MOSFET was not demonstrated
until 1955.
EE130/230A Fall 2013
Lecture 19, Slide 2
3
Metal Oxide SemiconductorField Effect Transistor
(MOSFET)

• An electric field is applied normal to the
  surface of the semiconductor (by applying a
  voltage to an overlying electrode), to modulate
  the conductance of the semiconductor.
• Drift current flowing between 2 doped regions
  (source drain) is modulated by varying the
  voltage on the gate electrode.

Lecture 19, Slide 3
EE130/230A Fall 2013
R. F. Pierret, Semiconductor Device Fundamentals,
Fig. 17.1
4
Modern MOSFETs
Metal-Oxide-Semiconductor Field-Effect Transistor
Gate

• Desired characteristics
• High ON current
• Low OFF current

Source
Drain
Substrate
P. Packan et al., IEDM Technical Digest, pp.
659-662, 2009

• Current flowing between the SOURCE and DRAIN is
  controlled by the voltage on the GATE electrode

• N-channel P-channel MOSFETs operate in a
  complementary manner
• CMOS Complementary MOS

Lecture 19, Slide 4
EE130/230A Fall 2013
4
5
N-channel vs. P-channel
NMOS
PMOS
N
N
P
P

• For current to flow, VGS gt VT
• to form n-type channel at surface
• Enhancement mode VT gt 0
• Depletion mode VT lt 0
• Transistor is ON when VG0V

• For current to flow, VGS lt VT
• to form p-type channel at surface
• Enhancement mode VT lt 0
• Depletion mode VT gt 0
• Transistor is ON when VG0V

Lecture 19, Slide 5
EE130/230A Fall 2013
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Enhancement Mode vs. Depletion Mode
R. F. Pierret, Semiconductor Device Fundamentals,
Fig. 18.18
Enhancement Mode
Depletion Mode
Conduction between source and drain regions is
enhanced by applying a gate voltage
A gate voltage must be applied to deplete the
channel region in order to turn off the
transistor
Lecture 19, Slide 6
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CMOS Devices and Circuits

• When VG VDD , the NMOSFET is on and the
  PMOSFET is off.
• When VG 0, the PMOSFET is on and the NMOSFET
  is off.

Lecture 19, Slide 7
EE130/230A Fall 2013
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Pull-Down and Pull-Up Devices

• In CMOS logic gates, NMOSFETs are used to connect
  the output to GND, whereas PMOSFETs are used to
  connect the output to VDD.
• An NMOSFET functions as a pull-down device when
  it is turned on (gate voltage VDD)
• A PMOSFET functions as a pull-up device when it
  is turned on (gate voltage GND)

VDD
A1 A2 AN
Pull-up network
PMOSFETs only
input signals

F(A1, A2, , AN)
A1 A2 AN
Pull-down network
NMOSFETs only

Lecture 19, Slide 8
EE130/230A Fall 2013
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CMOS NAND Gate
VDD
A B F
0 0 1
0 1 1
1 0 1
1 1 0
A
B
F
A
B
Lecture 19, Slide 9
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CMOS NOR Gate
VDD
A B F
0 0 1
0 1 0
1 0 0
1 1 0
A
B
F
A
B
Lecture 19, Slide 10
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CMOS Pass Gate
A
Y
Y X if A
X
A
Lecture 19, Slide 11
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Qualitative Theory of the NMOSFET
VGS lt VT
The potential barrier to electron flow from the
source into the channel region is lowered by
applying VGSgt VT

• Inversion-layer channel is formed

VGS gt VT VDS ? 0 VDS gt 0
Electrons flow from the source to the drain by
drift, when VDSgt0. (IDS gt 0) The channel
potential varies from VS at the source end to VD
at the drain end.
EE130/230A Fall 2013
Lecture 19, Slide 12
R. F. Pierret, Semiconductor Device Fundamentals,
Fig. 17.2
13
MOSFET Linear Region of Operation

• For small values of VDS (i.e. for VDS ltlt VG?VT),
• where meff is the effective carrier mobility
• Hence the NMOSFET can be modeled as a resistor

EE130/230A Fall 2013
Lecture 19, Slide 13
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Field-Effect Mobility, meff

• Scattering mechanisms
• Coulombic scattering
• phonon scattering
• surface roughness
• scattering

EE130/230A Fall 2013
Lecture 19, Slide 14
C. C. Hu, Modern Semiconductor Devices for
Integrated Circuits, Figure 6-9
15
MOSFET Saturation Region of Operation
VDS VGS-VT VDS gt VGS-VT

• When VD is increased to be equal to VG-VT, the
  inversion-layer charge density at the drain end
  of the channel equals 0, i.e. the channel becomes
  pinched off
• As VD is increased above VG-VT, the length DL of
  the pinch-off region increases. The voltage
  applied across the inversion layer is always
  VDsatVGS-VT, and so the current saturates.

ID
VDS
EE130/230A Fall 2013
Lecture 19, Slide 15
R. F. Pierret, Semiconductor Device Fundamentals,
Figs. 17.2, 17-3
16
Ideal NMOSFET I-V Characteristics
EE130/230A Fall 2013
Lecture 19, Slide 16
R. F. Pierret, Semiconductor Device Fundamentals,
Fig. 17.4
17
Channel Length Modulation

• As VDS is increased above VDsat, the width DL of
  the depletion region between the pinch-off point
  and the drain increases, i.e. the inversion layer
  length decreases.

If DL is significant compared to L, then IDS will
increase slightly with increasing VDSgtVDsat, due
to channel-length modulation
IDS
VDS
EE130/230A Fall 2013
Lecture 19, Slide 17
R. F. Pierret, Semiconductor Device Fundamentals,
Figs. 17.2, 17-3
18
Body Bias

• When a MOS device is biased into inversion, a pn
  junction exists between the surface and the bulk.
• If the inversion layer contacts a heavily doped
  region of the same type, it is possible to apply
  a bias to this pn junction.

N poly-Si

• VG is biased so that surface is inverted
• n-type inversion layer is contacted by N region
• If a bias VC is applied to the channel, a
  reverse bias (VB-VC) is applied between the
  channel and body

SiO2
N
p-type Si
EE130/230A Fall 2013
Lecture 19, Slide 18
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Effect of VCB on fS, W and VT

• Application of a reverse body bias ?
  non-equilibrium
• ? 2 Fermi levels (one in n-type region, one in
  p-type region) are separated by qVBC ? fS is
  increased by VCB
• Reverse body bias widens W, increases Qdep and
  hence VT

EE130/230A Fall 2013
Lecture 19, Slide 19