CS402

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CS402

• PPP 2
• MIPS BASIC INFORMATION
• By George Koutsogiannakis

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• The MIPS microprocessor is developed by MIPS
  Technologies Inc.
• A company founded in 1984 by a group of
  researchers from Stanford University.
• http//www.mipstechnologies.com
• There are 2 basic architectures MIPS32 and
  MIPS 64
• It is a RISC processor which stands for
  Reduced Instructions Set Computer.

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• MIPS can be little-endian or big-endian
  depending on the machine it is used.
• Little-endian means that the in a 4-byte
  word (32 bits) the Bytes are arranged as
  follows
• Byte
• Big-endian arrangement of bytes
• Byte

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When configured in big-endian order, byte 0 is
always the least-significant (right-hand) byte.
For example assume 4 words (32 bits each -4 bytes
each). The arrangement in memory of the 16 bytes
then is as follows
Figure 1
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Questions Which is the first words address
(least significant word)? Why memory
word address starts at 12?
Exercise Draw the same figure for little-endian
order
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There are two MIPS architectures MIPS32 and
MIPS64. We will concentrate on MIPS 32.

• Architecture refers to the instruction
  set, registers and other state, the exception
  model, memory management,virtual and physical
  address layout, and other features that all
  hardware executes (e.g. pipelining is an
  architecture issue)
• Implementation refers to the way in
  which specific processors apply the architecture
  (e.g. How caching works is an implementation
  issue).

There is a main processor and two
co-processors-each with their own set of registers
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Figure 2- MIPS 32
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PIPELINE
A pipeline is divided into the following discrete
parts, or stages Fetch Arithmetic
operation Memory access Write back
As a result in the parallel pipeline
implementation a number of instructions can be
In the pipeline simultaneously.
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• Questions
• How many instructions have finished execution in
  7 clock cycles?
• What if we had super pipelining where each stage
  takes half a cycle?
• How many instructions are then finished in 7
  cycles?
• What problems can pipeline present? See lab 2.
  Issue of delay.