Arithmetic Logic Functions

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Chapter 5

• Arithmetic Logic Functions

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This Chapter..

• We will be looking at multi-valued arithmetic and
  logic functions
• Bitwise AND , OR, EXOR, SHIFT etc Logic
  functions
• ADD, SUBTRACT, etc. Arithmetic functions

3
Iterative Functions and circuits

• Multi-bit logical functions (AND, OR, etc.) have
  functional independence between bits
• E.G. for a multi-bit AND where we want to find F
  A. B we have
• On the other hand, Arithmetic functions DO have
  dependence bit to bit (carry or borrow)
• The functions are the same at each bit position
  but dependent on the previous bit
• These functions are known as ITERATIVE

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Iterative Functions
Bi
Ai
Bi-1
Ai-1
B0
A0
Bn-1
An-1
Xi
Xi-1
X0
Xn-1
. . .
. . .
cell or stage i-1
cell or stage i
cell or stage n-1
cell or stage 0
Yi
Yi-1
Y0
Yn-1
. . .
. . .
Fi
Fi-1
F0
Fn-1
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Networks for Binary Addition
Half Adder - adds two bits together generates
sum and carry
Half-adder Schematic
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Networks for Binary Addition
Full Adder - adds three bits, one being a carry
bit
B0
A0
B1
A1
B2
A2
B3
A3
stage 0
stage 1
stage 0
stage 0
C1
C2
C3
C4
C0
Cascaded Multi-bit Adder
S0
S1
S2
S3
usually interested in adding more than two bits
this motivates the need for the full adder
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Networks for Binary Addition
Full Adder
S Cin xor A xor B Cout B Cin A Cin A B
But we can also write in long form ABCinABCi
nAB Cin (A xor B) A B
x
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Networks for Binary Addition
Full Adder/Half Adder implementation
Standard Approach 6 Gates
A
A
B
B
Cin
Cout
S
Cin
A
B
Alternative Implementation 5 Gates
Cout A B Cin (A xor B)
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Networks for Binary Addition
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Parallel(Ripple-Carry) Adder
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Parallel Adder-Subtractor

• Parallel Adder-Subtractor with 2s complement
  numbers
• To subtract, we take the 2s complement of the
  second number and add
• To take 2s complement use the approach Take 1s
  complement(Complement bit by bit) and add 1.
• To add 1, we will use the carry-in to the
  rightmost FA.
• Assume a select line called Add/subtract

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Networks for Binary Addition
Parallel Adder/Subtractor - assumes 2s
complement representation
2x1 mux
Remember subtraction is the same as taking the
2s complement and adding,so if add/subtract1,
complement b and add 1 from the rightmost Cin
A - B A (-B) A B 1
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Networks for Binary Addition

• The Propagation Delay in Above Circuit
• 3 gate delays for each full adder, but waits for
  2 gate delays
• For a 32 bit adder/subtractor, longest total
  delay is
• 3221 65 gate delays(will show in the
  next slide)
• Too long-should be a shorter way
• Assume A, B and C0 are presented to the input at
  the same time and all gates have the same delay

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Networks for Binary Addition
Carry Lookahead Circuits - making things fast
Calculated in parallel
late arriving signal
_at_N2
two gate delays to compute Cout
Critical delay the propagation of carry from low
to high order stages
4 stage adder
final sum and carry
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Networks for Binary Addition
Carry Lookahead Logic
Idea each carry can be expressed in terms of Ai,
Bi and C0
Carry Generate Gi Ai Bi must
generate carry when A B 1 Carry Propagate Pi
Ai xor Bi carry in will equal carry out
here
Sum and Carry can be reexpressed in terms of
generate/propagate
Si Ai xor Bi xor Ci Pi xor Ci Ci1 Ai Bi
Ci (Ai xor Bi) Ci1 Gi Ci P i
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Networks for Binary Addition
Carry Lookahead Logic
Reexpress the carry logic as follows
C1 G0 P0 C0 C2 G1 P1 C1 G1 P1 G0
P1 P0 C0 C3 G2 P2 C2 G2 P2 G1 P2 P1 G0
P2 P1 P0 C0 C4 G3 P3 C3 G3 P3 G2 P3
P2 G1 P3 P2 P1 G0 P3 P2 P1 P0 C0
Each of the carry equations can be implemented in
a two-level logic network Variables are
the adder inputs and carry in to stage 0!
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Networks for Binary Addition
Carry Lookahead Implementation
Adder with Propagate and Generate Outputs
Increasingly complex logic
C0
G3
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Networks for Binary Addition
Carry Lookahead Logic
Cascaded Carry Lookahead
Carry lookahead logic generates individual carries
sums computed much faster
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Partial Full Adder
Ripple Carry adder
Carry-save adder
Carry-lookahead unit
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Networks for Binary Addition

• Propagation Delay in CLA Adder
• Assume a 4-bit adder
• Since each carry will be generated in with a
  2-level And-or network, there will be a delay of
  2 in CLA unit
• Other delays 2 in PFA
• So total delay 4
• Ripple carry delay was 8

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• When the number of bits increase, the savings
  become more appearent but the CLA fan-in will
  increase unacceptably
• What to do? Use cascaded approach

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Networks for Binary Addition
Carry Lookahead Logic
Cascaded Carry Lookahead
4 bit adders with internal carry
lookahead second level carry lookahead unit,
extends lookahead to 16 bits
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BCD Addition
Decimal digits 0 thru 9 represented as 0000 thru
1001 in binary
Addition
5 0101 3 0011 1000 8
5 0101 8 1000 1101 13!
Problem when digit sum exceeds 9
Solution add 6 (0110) if sum exceeds 9!
5 0101 8 1000 1101 6
0110 1 0011 1 3 in BCD
9 1001 7 0111 1 0000 16 in
binary 6 0110 1 0110 1 6 in BCD
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BCD Addition
Adder Design
Add 0110 to sum whenever it exceeds 1001 (11XX or
1X1X)
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Incrementing and Decrementing by 1

• Use value fixing
• If you want S A1, then use adder/subtractor
  as
• A A, B0 Cin 1, function add
• How about S A-1?
• AA, B 00001, Cin0, Fn subtract
• Or, B1111111, Cin0, fn add
• May have inc/dec in the same circuit
• Make at home

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Multiplication and Division by Constants

• Shift function a word can be shifted right or
  left as many positions as you like with proper
  circuitry
• For a binary number, shifting left one digit
  means dividing by 2! Shifting right means
  multiplying by 2!
• But be careful with inserted digits.
• Will study later with shift registers.