AMICSA

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AMICSA
Methodologies for designing radiation hardened
Analog to digital converters for space
applications. DUTH/SRL George Kottaras, E.T.
SarrisNick, Stamatopoulos
DUTH/SRL
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AMICSA

• ADCs are very critical in space applications.
  (needed in every subsystem, telemetry,
  housekeeping, instrumentation, etc)
• Currently there is a high demand for ADCs and at
  the same time a lack of availability
• Commercial ADCs suffer from radiation effects
• TID effects
• SEE effects

DUTH/SRL
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AMICSA

• Main Radiation Effects in the ADCs.
• Analog components suffer from TID effects
• Digital components suffer from SEE effects.
• RADIATION EFFECTS ON ADCs ARE VERY TECHNOLOGY
  DEPENDENT.

DUTH/SRL
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AMICSA

• SOLUTIONS AGAINST TID
• Use deep submicron technologies
• Use enclosed geometry transistors.

TID effects are nearly cancelled.

• Potential Problems
• Deep submicron technologies need low Vdds
• Enclosed geometry transistors design rules
• 90deg bend gate is not allowed by most
  technologiesgt More complex designs
• Matching of ELTs is an important issue.

DUTH/SRL
GK
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AMICSA

• SOLUTIONS AGAINST TID
• Select appropriate topology for increasing
  radiation hardness.

DESIGN RULES FOR SELECTING A TOPOLOGY

• Minimum number of analog comparators (SA, S?), if
  possible.
• The comparator is most sensitive circuit in the
  ADC design. Needs autozeroing to cancel the
  effects.
• Rely on passive components for voltage/current
  division
• Resistors are preferred since they are immune
  to TID.
• Perform autozeroing in the digital domain, if
  possible.
• The autozeroing circuits will be more immune to
  TID.

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AMICSA
SOLUTIONS AGAINST TID
DESIGN RULES FOR ADC peripherals
Usually all ADCs are accompanied by some
peripherals such as S/H amplifiers,
instrumentation amplifiers, voltage references,
etc. Design having in mind that the smaller the
common mode variation of the input of the
amplifiers, the more TID immune the design is
going to be. For example, Amplifier A will be
more radhard than amplifier B.
Constant CM
Non Constant CM
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AMICSA
SOLUTIONS AGAINST TID
Autozeroing
Radiation Induced errors are inevitable no matter
of the design. The strategy is to compensate for
them. This step is called autozeroing.
Two possible ways to autozero

• Digital Autozero
• Somehow the TID induced offset is quantized and
  then digitally removed from the output code of
  the ADC.
• Analog Autozero
• Perform autozero function on the comparator/s by
  means of an error amplifier.

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AMICSA
SOLUTIONS AGAINST TID
Analog Autozeroing

• Analog autozeroing involves adding an offset
  value in the comparator input so as to cancel
  that TID induced offset. It is frequently used in
• Flash ADCs
• Pipeline ADCs
• An extra phase is required so that autozeroing
  can be performed.

DUTH/SRL
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AMICSA
SOLUTIONS AGAINST TID
Analog Autozeroing
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AMICSA
SOLUTIONS AGAINST TID
Digital Autozeroing

• Digital Autozeroing is applied on the output code
  of the ADC.
• Can be easily applied in
• S? ADCs
• Successive Approximation ADCs
• Current cyclic ADCs.
• Usually oversampling is involved.

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AMICSA
A Rad-Hard Successive digitally autozeroed
Successive Approximation ADC
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AMICSA

• It consists of
• 2 DACs sharing the same resistive string
• a comparator
• a successive approximation state machine (SASM),
  
• a temporary register and a subtractor circuit.
• The comparator, along with the SASM and one of
  the two DACs form the successive approximation
  ADC.
• The temporary register, the subtractor and the
  auto zeroing DAC (AZ-DAC) are utilized to perform
  the digital auto-zeroing function on the ADC.

DUTH/SRL
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AMICSA
When no auto-zeroing is selected the device works
as a nominal 10-bit successive approximation ADC.
When auto-zeroing is selected, two analogue to
digital conversions take place sequentially and
the final result is a combination of the two
conversions. In the first analogue to digital
conversion, the analogue input is converted by
the successive approximation ADC to a digital
word (OC1), stored to a temporary memory
location, after being shifted one position left,
and fed to the AZ-DAC. In the second A/D
conversion the analogue input is isolated and the
output of the AZ-DAC, which is the result of the
first A/D, is converted to a digital word (OC2)
by the successive approximation ADC. The output
code (OC) comes from the following subtraction
OC2OC1-OC2
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AMICSA
A Rad-Hard Successive digitally autozeroed
Successive Approximation ADC
DUTH/SRL
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AMICSA
A Rad-Hard Successive digitally autozeroed
Successive Approximation ADC
Assume that in the CM of interest the comparator
has developed offset (in LSBs) off. The result
from the first conversion would be
OC1OCidealoff
The second conversion would yiled a code equal to
OC2OCidealoffoff
The final result wuld be eual to
OC2OC1-OC2OCideal
Offset has been cancelled
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AMICSA
Use of the above architecture to produce a
subranging converter
101 bits
11 bit Successive Approximation ADC
VDAC
Large common mode so Analog AZ is
required Special AZ technique developed
Vin
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AMICSA

• SOLUTIONS AGAINST SEEs
• Large FFs in the state machine
• P-N good separation gt full custom layout
• Use of guardrings gt full custom layout
• Watchdog counters to reset the ADC incase of
  SEUs.

DUTH/SRL
GK