Roadmap toCompany Critical Mission Success Milestone

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A 0.15?M Radiation-Hardened Antifuse Field
Programmable Gate Array Technology
Leonard Rockett1, Dinu Patel1, Steven Danziger1,
Balwinder Sujlana1, Les Palkuti2, John
McCollum3, J.J. Wang3, Brian Cronquist3, Farid
Issaq3 and Frank Hawley3 1BAE SYSTEMS, 9300
Wellington Road, Manassas, VA 20110-4122 2Defense
Threat Reduction Agency, 6801 Telegraph Rd,
Alexandria VA 22310 3Actel Corporation, 2061
Stierlin Ct, Mountain View, CA 94043
The RH AX250-S production installation effort is
sponsored by the Defense Threat Reduction Agency.
MAPLD 2005 / E134
Rockett
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Outline

• Introduction
• Process Development
• Base Radiation Hardened Process
• Anti-fuse
• High Voltage Transistor
• Radiation Results
• Total Ionizing Dose
• Single Event Gate Rupture
• Single Event Upset
• Summary

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Introduction

• FPGA products are used extensively in space
  systems
• Since 1996, BAE Systems has supplied Actel over
  25,000
• ONO anti-fuse based Rad Hard FPGAs
• Next generation radiation hardened Metal to
  Metal (M2M)
• anti-fuse based FPGA is needed for advanced
  military and
• space applications
• Actel and BAE SYSTEMS are developing next
  generation RH
• FPGA, leveraging
• Our decade long collaboration
• Actels proven rad tolerant FPGA design
• BAE Systems newly modernized rad hard CMOS
• technology capabilities.

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RHAX250-S Approach
RH15 Radiation Hardened Base Process
Radiation Hardened FPGA AX250-S
Final stages

• FPGA
• Unique features
• High Voltage Tx
• Anti-fuse

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Off-Current Total Ionizing Dose Response for
3.3V NFET Transistor
Unhardened Sample
Hardened Splits
High voltage NFET transistors exceed hardness
requirements
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Total Dose Response for Parasitic Isolation (STI)
Device
Unhardened Sample
Hardened Splits
High voltage transistor isolation exceeds
hardness requirements
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TID Radiation Testing - RH15 High Speed CktRH15
Base process

• Gamma-Cell
• Dose-rate 46rd(SiO2)/s
• Maximum Dose 2Mrd(SiO2)
• Room temperature
• Known pattern (all 1s) clocked into circuit
• Vdd(Core) 1.65V
• Vdd(I/O) 3.6V

Error-bars are minimum and maximum of dataset
DC parametric shows stability to
2Mrd(SiO2) Idd(Q)-Core shows very little change
in value after 2Mrd(SiO2)
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TID Radiation Testing on High Speed CktRH15 Base
process
Error-bars are minimum and maximum of dataset
RH15 High Speed Circuit shows gt1GHz performance
both pre- and post-irradiation (2 Mrd(SiO2))
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TID Testing on 4Mb SRAM RH15 Base process
DC AC parameters and functionality show very
little change after 2Mrd(SiO2)
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RHAX250-S Approach
RH15 Radiation Hardened Base Process
Radiation Hardened FPGA AX250-S
Final stages

• FPGA
• Unique features
• High Voltage Tx
• Anti-fuse

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RHAX250-S Product Road Map
RTAX250-S
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Process Design Rule Development

• RTAX250-S design transferred to BAE

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Process Integration / Technology Validation
Completing
First FPGA lots started
Product Demonstration
Actel-BAE collaboration supported by DTRA
QML Qualification
RHAX250-S
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RHAX250-S FPGA Product
RHAX250-S Product Features
M2M Antifuse Structure
M2M antifuse
Radiation Hardness Features
Total Ionizing Dose ? 1Mrad (Si) Single Event
Latchup Immune Single Event UpsetLET gt
37MeV-cm2/mg SETe-RAM lt 1E-10 e/b-d
(EDAC) TMR-hardened registers.
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SEM Cross-section of Metal to Metal Anti-fuse
TiN
TEOS
Amorphous Si
TiN
Ti
W- Stud
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Anti-Fuse Time Dependent Dielectric breakdown


Anti-fuse element TDDB meets or exceeds
requirements
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PFET High Voltage Transistors Data
High voltage PFET process optimization is very
encouraging
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NFET High Voltage Transistor Data
High voltage NFET optimization meets the
specifications requirement
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SEDR Testing - Actels Prototype RTAX250

• Plotting power supply current (ICC) versus run
  time and checking
• ICC, there was no occurrence of SEDR in any
  test run. The
• maximum LET used at BNL was 60 MeVcm2/mg, and
  the
• maximum LET used at TAMU was 54 MeVcm2/mg.
• Normal incidence is worst case for SEDR, so the
  worst case
• testing was performed in test runs with high
  LET ions.

ICCA has small fluctuations but no significant
permanent jumps, which would be the signature of
SEDR.
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Triple Modular Redundant Flip-Flop (K-Latch)
Triple Modular Redundant (TMR) Latch used for SEU
Hardness
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Hard-wired TMR Flip-Flop Cross-section per bit
SER 1.96x10-11 upsets/bitday
Logic with TMR latches exceed hardness
requirements
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Summary

• BAE Systems and Actel Corporation continue their
  long successful collaboration
• 0.15?m radiation-hardened 250K gate FPGA for
  space in development
• Same form, fit, and function as commercial RT
  version
• RH process Total ionizing dose data meets target
  
• Single Event Upset test results of TMR-hardened
• flip-flop designs meet target, no occurrence
  of
• SEDR observed during heavy ion testing
• Full suite of radiation testing planned for
  Radiation Hardened product demonstration

Product installation efforts are progressing well
toward completion in early 2006, with qualified
parts available in late 2006 The RH AX250-S
production installation effort is sponsored by
the Defense Threat Reduction Agency.
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