CHDStd and Related Standards Efforts

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CHDStdand Related StandardsEfforts
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The Physics of Small
Technology Trend
The Physics
b
Decreasing Gate Length
Increased file file sizes Increased Power
50 m transistors by 2000

Decreasing Metal Pitch
Coupled effects Reliability issues
GHz range in by 1999


Decreasing Clock Cycle
Inductive effects Reflections
GHz range by 1999


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Harness the Physics of Small

• Analysis Time ? to Design Change (design
  cycle time)
• Minimize Data Redundancy (data
  management)
• Maximize Design Reuse (productivity)
• Minimize File Translation (cycle time)

Ability to integrate tools of choice
Density

• Full Scope Model (complex analysis)
• Common Analysis Engine (convergence)
• Concurrent Design and Analysis (cycle
  time)
• Supplier Technology Characterizations
  (accuracy)

Frequency
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Goals

• Develop an open industry wide model for chip
  design and analysis data (CHDStd) -
  comprehensive data scope and unambiguous API
  access
• Demonstrate value proposition with SEMATECH
  companies
• Achieve commercial adoption of database servers
  and EDA applications using the specification
• Gain formal standards accreditation

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CHDStd Elements
Design Library
Process Library
Cell Library
Netlist
Delay
Wire/Via/Pad Models
Power
Layer Rules
Physical
IDM API
PDL API
Function
OLA API
Constraints
Electrical
Properties
Layout
Electrical Specs.
Physical
Design
Analyze
Common Datamodel
Concurrent Comm.
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Effective Integration of All
Methodology
Flow Data Management
EDA Applications
CHDStd
Common Data Access
Data Repository
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CHDStd

• Comprehensive Data Scope
• Design Library (IDM)
• hierarchical connectivity network for the design
• physical characteristics (wires, shapes, area,
  placement, constraints, etc.)
• electrical characteristics (parasitics, delays,
  constraints, etc.)
• Technology Library (OLA)
• delay and power calculation, logic function,
  block attributes
• cell physical properties (OLA-P)
• Process Definition Library (PDL)
• physical and electrical models, design rules,
  constraints
• process characterization (SIPPs)
• Engineering Change Order (ECO) language
• Full Application Program Interface (API)

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Design Library (IDM)
Interface
Placement
Wiring
Views
Physical
Constraints
Layout
Electrical
Selectable
Incremental
Folded
Occurrence
Hierarchical
Netlist
Load/Save
Persistent Store
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IDM Highlights

• Proven
• Based on technology in use at IBM
• Extensible
• Property, Group, Rule Box
• Hierarchical
• Full hierarchy preserved on both folded and
  occurrence models
• Incremental
• Application selectable data and views
• Formal mechanisms defined for incremental support
• Concurrent
• Facilities to manage EDA design and analysis
  applications working on same design library
  concurrently, reducing costly sequential steps

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Cell Library (OLA)

• Open Library API - simple cells through complex
  cores
• Delay and Power calculations
• Block function
• Block characteristics used for Synthesis, Test,
  etc.
• Block Physical characteristics
• Based on LEF Data Model
• Direct Access Compiled
• IP Protection
• Speed
• Size
• ASCII Equivalent (ALF) from OVI
• Diagnosis and repair
• Based on DPCS (IEEE 1481) Architecture

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OLA - Physical

• Adds cell physical characterization to OLA
• Extended OLA API
• Extended ALF file format
• Based on proven LEF data model
• Transfer of LEF format from Cadence to enhance
  migration

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OLA-Physical
Strategic- Flow
DPCM
Translate
Compile
DCL
EDAApps
TimingPowerFunction Physical
API
ALF
Strategic- Field Repair
Reader
Ttranslate
Migration
LEF
Today
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Process Definition Library (PDL)

• Describes technology characteristics and
  constraints
• Technology design groundrules
• Chip background and image descriptions
• Design constraints

Technology/Package Wiring layers Placement
area Wiring area I/O area Terminal
placement Wiring models constraints Via
models Power models constraints Placement
models constraints Pre-placed structures
Application Areas Placement Power
Constraints Cell size, placement and wiring
porosity, .. Net - length, resistance,
capacitance, delay,.. Port and wiring constraints
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SIPPs

• A single technology characterization
• Tool-independent
• Electrically accurate
• Flexible for different abstraction levels
• Extensible enough for future processes technology
• Advantages
• Supplier characterizes process in one format
• Tools have standard access to characterization
• Designer gets better correlation of results
• Design can use multiple extractors in flow
• Allowing selective accuracy vs. speed tradeoffs
• Based on technology from Frequency Technology and
  OEA international

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SIPPs Physical Model Concept
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CDL

• Layer by Layer Description of substrate,
  dielectrics, and metal
• Metal dimensions and resistivities
• Dielectric thicknesses and permitivity
• Metal and trench coatings
• Dimension losses
• Air gaps
• Temperature and spacing variations
• Process variations

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CHDStd Plug and Play
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Integration Use Models
Interfaced Functions
Integrated Functions
.
Application (Private Model)
Application (Private Model)


Application

Application
Map
Application
Translate
CHDStd API
Operational Memory or Data Repository
API is point of integration rather than
translated files
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CHDStd Reference Server
Add Delete Traverse
API
Application
Memory Structures
Load Save
API
File Repository
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Reference Server Use Model Options
CHDStd Reference Server
Customer Developed Server
Reference API with Customer Repository
Add Delete Traverse
API
Add Delete Traverse
API
Add Delete Traverse
API
Memory Structures
Memory Structures
Memory Structures
Application
Application
Application
Load Save
API
Load Save
API
Load Save
API
File Repository
File Repository
File Repository
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Engineering Change Orders (ECO)

• Defines delta modifications to a design
• Add, delete and modify cells, ports or nets as
  well as their placement and properties
• Allows incremental design changes between
  sessions and across design teams
• Facilitates managed EC process across the design
  team

Net addNet deleteNet reconnectNet
Cell addCell deleteCell moveCell swapCells discon
nectCell
Port addPort deletePort movePort swapPorts connec
tPort disconnectPort
Other changeChildDef updateCellProperty updatePor
tProperty updateNetProperty
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Putting it Together - CHDStd
Cell Library
Delay Power Function Physical
OLA
Process Library
Process Variation Modeler
Technology/Process Parameters
PDL
IEEE 1481
Design Planner
Extractor(s)
Place Route
Synthesis
Timing
IDM
Design Model
Transistor Level Timing Analysis
Power Network Analysis
Signal Integrity Verification
Design Library
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Want More Information?

• Specifications at
• www.si2.org/CHDStd
• www.si2.org/ola
• www.si2.org/sipps