A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in CT SDM

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A Fixed-Pulse Shape Feedback Technique with
Reduced Clock-Jitter Sensitivity in CT SDM

• Yang Jiang, Kim-Fai Wong, Chen-Yan Cai,
• Sai-Weng Sin, Seng-Pan U and Rui. P. Martins
• Analog and Mixed Signal VLSI Laboratory
• University of Macau

Presenter Yang Jiang
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Contents

• Introduction to Clock-Jitter in CT SDMs
• Existed Solutions
• Fixed-Pulse Shape Feedback Technique
• CT SDM Design Example
• Simulation Results
• Conclusion

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Introduction
Clock-Jitter in CT SDM
Clock-jitter effect is worse in RZ case !
Pulse Width (PW) Random Variation
White Noise in every clock cycle
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Existed Solutions
Shaped-Feedback Waveform (RZ)
Principle Minimize the FB pulse at the end of
the feedback phase to reduce the PW variation
effect.
Traditional
SCR
SCSR
PW variations Peak current vv
PW variations vv Peak current Implementation
v
PW variations v Peak current v Implementation
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Fixed-Pulse Shape Feedback
Fixed-Pulse Shape (RZ)
Principle Fix the FB PW independent of the
jittered clock.
Traditional
Benefit Generate precise FB pulse with
appropriate peak current.
Proposed Technique
PW variations Peak current vv
PW variations vv Peak current v Implementation vv
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Fixed-Pulse Shape Feedback
Proposed RCDD Structure
Idea Generate a fixed time interval based on RC
discharge process.
Clock Independent
RC Discharge Detection (RCDD) Circuit
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Fixed-Pulse Shape Feedback
RC Variation Effect
FB RC Variation Insensitive
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Fixed-Pulse Shape Feedback
RC Variation Effect
Td
Tr
FB PW
Leave enough margin for Tr .
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Fixed-Pulse Shape Feedback
Clock-Jitter Insensitivity
Clock-jitter Immune !
?Tr do not affect FB PS.
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CT SDM Design
Design Specifications
Loop Quantizer Signal Bandwidth Sampling Frequency OSR FB Type
2nd Order LP CIFB 1-bit 1.92 MHz 250 MHz 64 RZ
Implement Proposed Tech. / ELD Tolerant
10-bit
WCDMA
Stability
Linearity
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CT SDM Design
Circuit Implementation
- RC Integrators - SR Feedback - Dynamic
Comparator
- VDD 1 V -
VCM 500 mV
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CT SDM Design
Feedback DAC
RCDD Circuit
Polarity Judgment
Switched-Resistors
? ß Tfb sj sRC
0.2 0.7 0.5TS 10TS 40
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Simulation Results
Simulated PSD
Test input -2dBFS _at_ 100kHz
76dB
56dB
81dB
Traditional 0 jitter RCDD 1 jitter
Traditional 1 jitter
1 clock-jitter effect
No clock-jitter effect
SNDR 63dB, SFDR 76dB SNDR 43dB, SFDR
56dB
SNDR 67.5dB, SFDR 81dB
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Simulation Results
Clock-Jitter Sensitivity
62dB (10-bit)
30dB
0.08
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Test input -2dBFS _at_ 100kHz
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Simulation Results
Performances Summary
CT SDM Performances
RCDD DAC Traditional DAC
Technology 65 nm CMOS 65 nm CMOS
Supply Voltage 1 V 1 V
Input Range (Diff) 1.6 Vpp 1.6 Vpp
Signal BW / Sampling Rate 1.92 MHZ / 250 MHz 1.92 MHZ / 250 MHz
OSR 64 64
SNDR (0 jitter) / SNDR (1 jitter) 65dB / 63dB 67.5dB / 43dB
SFDR (0 jitter) / SFDR (1 jitter) 79dB / 76dB 81dB / 56dB
THD (0 jitter) / THD (1 jitter) 78dB / 78dB 82dB / 58dB
Total Power 4.54 mW 4.03 mW
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Conclusion

• A Feedback technique with reduced clock-Jitter
  sensitivity is proposed.
• Using RC discharge detection (RCDD) technique to
  fix FB pulse-shape.
• Accurate FB can be achieved (RC-variation
  tolerant).
• Full transistor-level CT SDM was designed.
• Simulation result verified the effectiveness of
  the proposed technique.

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Reference

• SCSR M. Anderson and L. Sundstrom, Design and
  measurement of a CT S? ADC with
  switched-capacitor switched-resister feedback,
  IEEE J. Solid-State Circuit, vol. 44, no. 2, pp.
  473-483, February, 2009.
• SCR M. Ortmanns, F. Gerfers, and Y. Manoli, A
  continuous-time S? modulator with reduced
  sensitivity to clock jitter through SCR
  feedback, IEEE Trans. Circuits System I, Regular
  Paper, vol. 52, no. 5, pp. 875884, May 2005.

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• THANK YOU
• Q A

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