Mixed-size VLSI Placement

1
Mixed-size VLSI Placement

• Igor L. Markov,
• Advanced Computer Architecture Lab

2
Outline

• Intro algorithms for chip design
• Large-scale placement in VLSI
• Design objectives (power) and constraints(routabi
  lity, delay)
• Placement with chunky blocks (memories,
  arithmetic circuits, Intellectual Property, etc)
• Fixed-outline floorplanning (block-packing)
• Sequence pair representation
• Mixed-size placement

3
Intro Algorithms for Chip Design

• Modern hardware cant be designed by hand
• Major problem scale, 108 gates(think of wire
  routing for even 10K gates)
• Major problem technology considerations
• Scale emphasizes asymptotic complexity of
  algorithms
• Technology considerations pose new algorithmic
  problems
• Over 80 of circuit delay is in wires
• Wires are responsible for a large of power

4
Large-scale Placement

• Find locations of things
• E.g., logic gates placed in 2d (hundreds of
  millions)
• Minimize interconnections(communication delays?)
• Total (average)? Max? Other Lp-norms? Overall
  performance?
• Constraint things have sizes and cannot
  overlap
• Constraint interconnections must be routable

5
VLSI Placement Examples
6
Total Dynamic Power Breakdown (Intel Centrino)
Global clock included
Source Intel, Feb 2004
7
Impact of Computer-Aided Design

• A single piece of software may improve
  delay/power of a chip by over 10
• Such improvements will show in many chips
• Top CAD tools sell for over 100,000/license
• Commercial CAD tools areoften used as black
  boxes
• Relatively safe to evaluate
• Relatively easy adoption(compare to the recent
  Al?Cu change)
• Fundamental CAD problems (partitioning
  placement, etc) are tech.-independent

8
Standard-cell vs. Mixed-size
9
Mixed-size Placement

• Reuse of intellectual property in
  chipsmacro-gates large rectangular blocks
• MPEG decoders
• On-chip memories
• Caches, communication buffers
• Analog components
• On-chip radios, analog-to-digital converters

10
System on Chip (SoC) context

• Mixed-signal designs
• Different blocks designed by different companies
• SoC integration
• Hierarchical vs. Flat
• Need for mixed-size,fixed-outline placers

11
Standard-cell vs. Mixed-size
12
Metrics and Constraints

• Metrics
• Total wirelength (affects power)
• Total placement runtime (turn-around time)
• Constraints
• All rectangles must fit into the placement area
• Rectangles cannot have overlaps
• All wires must be routable
• Additional wish list for algorithms
• Simplicity and predictability

13
Cadence-recommended Mixed-size Flow for SEDSM

• SEDSM places blocks at the periphery
• Designer manually removes overlaps
• From now on, blocks are considered fixed
• QPlace is called to place standard-cells
• Otherwise, as our experiments show,
• Handling many large cells is not ideal in QPlace

14
SEDSM Output
15
Mixed-size Placement Previous Work

• Continuous optimization techniques
• Force directed approaches
• Eisenmann, Johannes, DAC 98 mixed-mode
• Mo et. al, ICCAD 00 macros only congestion
• Are good with a lot of white-space in design
• Otherwise, designer must remove overlaps
• Combinatorial optimization techniques
• Particularly promising on constrained designs
• Nag et. al, DATE 98 macros only
• Adya Markov, ISPD 02 Min-cut Placement
• 
  Floorplanning
• Chang et. al, ASPDAC 03 Multi-level placement
• Madden et. al, ISPD 04 Min-cut placement
• 
  Post Placement Legalization

16
Kraftwerk Force-directed PlacerEisenmann
Johannes, DAC 98
ibm02
ibm03
17
CapoParquet Flow Adya Markov, ISPD 02
(Outline)

1. Generate initial placement using an
   arbitrary, min-WL standard-cell placer
2. Generate a fixed-outline floorplanning instance
   by physical clustering
3. Remove overlaps and generate valid macro
   locations using a fixed-outline floorplanner
4. Place small cells using standard-cell placer with
   macros considered fixed

18
High Temperature Annealing
Final Placement
Initial Placement
Floorplanned design
19
Low Temperature Annealing Try to maintain
initial macro locations
Final Placement
Initial Placement
Floorplanned design
20
Shredding Kraftwerk ECO Legalization
Initial Placement
Final Placement
21
mPG (Multi-level placement using SA)Chang et.
al, ASPDAC, 03
22
mPG
23
FengshuiMadden et. al, ISPD 04
Initial
Legalized
24
Our approach Integration of Placement and
Floorplanning

• Min-cut placement techniques
• Scalable can handle large number of objects
• Good at wirelength minimization
• Floorplanning techniques
• Can handle vastly different shapes and sizes of
  objects
• Not very scalable
• Our approach
• Tight integration of placement and floorplanning
  to solve the mixed-size placement problem
• Implies solving fixed-outline floorplanning
  problem

25
Global Placement by Recursive Bisection
etc.

• Our placer (Capo) very fast,typically produces
  routable placements,used in commercial CAD tools

26
Recursive Bisection Placement Fixed-outline
floorplanning
27
Fixed Outline Constraints

• Not an area minimization problem
• Rather a constraint satisfaction problem

?
?
y-span
x-span
28
Sequence Pair (SP) Representation

• Proposed by Murata et al. TCAD 97
• Two permutations of N blocks capturegeometric
  relations between each pair of blocks
• (ltabgt,ltabgt) ? a is to the left of b
• (ltabgt,ltbagt) ? a is above b
• Horizontal (Vertical) constraint graphs
• Edge a?b iff a is to the left of b (a is above b)
• Can compute packed block locationsusing a
  two-loop algorithm
• O(n2) complexity
• O(n log n) and O(n log log n) algos

Top
A
Right
Left
B
C
ltABC, BACgt
Bottom
29
Floorplan Slack
F
D
F
D
E
E
C
C
B
B
ltFEDBCA, ABFECDgt
A
A
ltFEDgt is the LCS
Left Packing
Right Packing
x-slack for block A x(Aright) x(Aleft)
x-Slack Computation
30
Example A Slack-based Move
Block with y-slack0
31
Objective Functions

• Main framework Simulated Annealing (SA)
• Need an objective
• Classical min-area objective appears inadequate
• Choose one of 3 objective functions
• Min area
• Min ? area ? WL
• Min ? area ? WL ? AR

32
Fixed-outline Floorplanningwith Simulated
Annealing

• Find target aspect ratio of fixed outline
• During annealing, track current aspect ratio
• Apply slack-based moves if current aspect ratio
  too far from target aspect ratio
• (targetAR currAR)/targetAR gt 0.005
• A sample slack-based move
• Find block A with zero slack in one dimension
• Find block B with large slack in other dimension
• Place A close to B
• Different slack-based moves are possible

33
Fixed-outline FPer Parquet(based on Simulated
Annealing)
Restart
?
current outline
S.A.
y-violation
S.A.
S.A.
?
x-violation
required outline
34
Fixed-Outline FP Results

• Without slack-based moves
• Not able to satisfy fixed-outline constraints (!)
• With slack-based moves
• Fixed-outline success rates for benchmark w 100
  blocks

35
Global Placement by Recursive Bisection
etc.
36
Mixed-size placement flow

• Variables queue of placement blocks
• While (queue not empty)
• Deque a block
• If (block has at least 1 large macro)
• Cluster std-cells into soft clusters
• Use fixedoutline floorplanner to find valid
  locations of macros in the block
• Fix macros and remove sites underneath the macros
• else if (small enough)
• Process end case
• else
• Bi-partition the block into smaller blocks
• Enque each child block

37
Final Output of Placement
38
Routed Design
39
Results
Kraftwerk
mPG
Fengshui
Capo1
Capo 2
Ckt WL Time WL Time WL Time WL Time WL Time
01 3.01 2m 3.01 9m 2.41 3m 2.92 5m 2.96 1.8m
02 7.58 9m 7.42 18m 5.34 5m 6.5 11m 5.93 4.6m
10 51.5 35m 43.6 86m 37.4 22m 47.5 68m 37.4 51m
15 73.7 93m 65.5 192m 52.4 87m 66.8 122m 61.1 56m
18 54.9 110m 50.7 220m 45.5 114m 57.2 158m 50.9 44m
40
Summary

• Mixed-size placement is a major open problem in
  VLSI placement
• Our main contribution is a set of methods that
  ensure non-overlapping placements
• Typically routable too
• Based on block-packing
• Our algorithms are fast
• There is clearly room for improvement
• Can techniques from AI search be useful?

41
Results