??????????? SoC Design Flow

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???????????SoC Design Flow Tools

• ???
• (Pao-Ann Hsiung)
• ?????????????
• (National Chung Cheng University, CSIE)
• http//www.cs.ccu.edu.tw/pahsiung/courses/soc/
• pahsiung_at_cs.ccu.edu.tw Class EA-204
• [phone] ext. 33119 Office EA-512

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What will you learn from this course?

• What is a System-on-Chip (SoC)?
• Motivation
• History
• State-of-Art
• What are the design issues?
• Complexity digital, analog, mixed, IP, memory,
• Hardware-software codesign
• Functional Verification full-chip, hw, sw,
• How to design and verify an SoC?
• Design Verification Flow
• Design Verification Tools

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Who should take this course?

• Interested in becoming a system
  (hardware-software) engineer
• Interested in designing SoCs
• EE background learn system design, embedded
  software design, verification
• CS background learn SoC architecture, embedded
  hardware design, verification
• Essential backgrounds C/C programming,
  computer architecture, OS

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Who should NOT take this course?

• Only wants course credits
• Only because SoC is popular
• Does not like research
• Does not like projects
• Does not like using tools or lab work
• Not creative (lack of new ideas)
• Yawns and goes to sleep when someone is talking
  about system design

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Reference Books (Design)

• Daniel D. Gajski et al., Specification and
  Design of Embedded Systems, Prentice Hall, 1994.
• Henry Chang et al., Surviving the SoC
  Revolution, Kluwer Academic Publishers, 1999.
• Bassam Tabbara et al., Function/Architecture
  Optimization and Co-Design of Embedded Systems,
  Kluwer Academic Publishers, 2000.
• Michael Keating, Pierre Bricaud, Reuse
  Methodology Manual, Kluwer Academic Publishers,
  2002.
• Frank Vahid, Tony Givargis, Embedded System
  Design, John Wiley Sons, Inc., 2002.
• Steve Furber, ARM System-on-Chip Architecture,
  2nd Edition, Addison Wesley, 2000.

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Reference Books (Verification)

• Prakash Rashinkar, Peter Paterson, Leena Singh,
  System-on-a-chip Verification, Kluwer Academic
  Publishers, 2001.
• Lionel Bening, Harry Foster, Principles of
  Verifiable RTL Design, Kluwer Academic
  Publishers, 2001.

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Course Syllabus Schedule

• Topic Week
• Introduction 1
• System Modeling 2 4
• Hardware-Software Codesign 5 7
• Mid-Term 8
• SoC Verification 9 10
• Configurable Processors 11
• SoC Testing 12 13
• Project Presentations 14
• Final Exam 15

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Course Grading

• Mid-Term Exam 30
• Final Exam 30
• Digital Camera Project 16
• 6 Labs 24

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Digital Camera Project

• Design a digital camera SoC with hardware and
  software (JPEG)
• Schedule
• Written Report May 31, 2005
• Presentation May 31, 2005
• Demonstration Before Final Exam
• Grade (total 16)
• Report 5, Presentation 5, Demo 6

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SIX Labs

• Familiarity with Tools
• Cadence SystemC/Verilog/VHDL simulators
• UML Editor and Simulator
• Mentor Seamless Co-Verification Environment (CVE)
• FPGA design tools
• Altera Quartus II v3.0, SoPC Builder
• Xilinx ISE Foundation, and other tools
• Coware ConvergenSC
• Tensilica Xtensa Configurable Processor

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Labs

• All 6 labs (total 24)
• Assignment last ½ hour
• Deadline after 2 weeks
• Grading faster?higher grades
• Demonstration contact TA
• TA ???, Ext. 23125, Lab EA305

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SoC Design Flow Tools

• ENJOY THE COURSE!!!