ECE260B

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ECE260B CSE241AWinter 2005Testing
Website http//vlsicad.ucsd.edu/courses/ece260b-
w05
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Outline

• Defects and Faults
• ATPG for Combinational Circuits
• ATPG for Sequential Circuits

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Fault models
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Fault Models
Most Popular - Stuck - at model
Covers many other occurring faults, such as opens
and shorts.
a, g x1 sa1 b x1 sa0 or x2 sa0
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Fault Models
a

• To detect an and-bridging
• Detect a s-a-0 and b 0
• Detect b s-a-0 and a 0
• To detect a transition fault
• Pattern 1 c 1
• Pattern 2 detect c s-a-1

and
b
c
good
1
bad
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Problem with stuck-at model CMOS open fault
Sequential effect
Needs two vectors to ensure detection!
Other options use stuck-open or stuck-short
models This requires fault-simulation and
analysis at the switch or transistor level -
Very expensive!
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Problem with stuck-at model CMOS short fault
Causes short circuit between Vdd and GND for
AC0, B1 Possible approach Supply Current
Measurement (IDDQ) but not applicable for
gigascale integration
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Exhaustive Algorithm

• For n-input circuit, generate all 2n input
  patterns
• Infeasible, unless circuit is partitioned into
  cones of logic, with lt 15 inputs
• Perform exhaustive ATPG for each cone
• Misses faults that require specific activation
  patterns for multiple cones to be tested

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Random Pattern Generation

• Flow chart for method
• Use to get tests for 60-80 of faults, then
  switch to D-algorithm or other ATPG for rest

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Fault simulation
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Boolean Difference Symbolic Method (Sellers et
al.)

• g G (X1, X2, , Xn) for the fault site
• fj Fj (g, X1, X2, , Xn)
• 1 j m
• Xi 0 or 1 for 1 i n

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Boolean Difference (Sellers, Hsiao, Bearnson)

• Shannons Expansion Theorem
• F (X1, X2, , Xn) X2 F (X1, 1, , Xn)
  X2 F (X1, 0, , Xn)
• Boolean Difference (partial derivative)
• Fj
• g
• Fault Detection Requirements (for g s-a-0)
• G (X1, X2, , Xn) 1
• Fj
• g

Fj (1, X1, X2, , Xn) Fj (0, X1, , Xn)

Fj (1, X1, X2, , Xn) Fj (0, X1, , Xn) 1

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Basic Terms, Path Sensitization

• Controllability the ease of controlling the
  state of a node in the circuit
• Observability the ease of observing the state of
  a node in the circuit

Goals Determine input pattern that makes a
fault controllable (triggers the fault, and makes
its impact visible at the output nodes)
sa0
1
Fault enabling
1
1
1
1
1
0
Fault propagation
0
Techniques Used D-algorithm, Podem
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5-Value Logic

• 0 binary 0 in both good and fault circuit
• 1- binary 1 in both good and fault circuit
• X dont care
• D binary 1 in good circuit, 0 in bad circuit
• D binary 0 in good circuit, 1 in bad circuit

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Primitive D-Cube of Failure

• Models circuit faults
• Stuck-at-0
• Stuck-at-1
• Bridging fault (short circuit)
• Arbitrary change in logic function
• AND Output sa0 1 1 D
• AND Output sa1 0 X D
• X 0 D
  
• Wire sa0 D
• Propagation D-cube models conditions under
  which fault effect propagates through gate

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Forward Implication

• Results in logic gate inputs that are
  significantly labeled so that output is uniquely
  determined
• AND gate forward implication table

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Backward Implication

• Unique determination of all gate inputs when the
  gate output and some of the inputs are given

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Path Sensitization Method Circuit Example

• Fault Sensitization
• Fault Propagation
• Line Justification

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Path Sensitization Method Circuit Example

• Try path f h k L blocked at j, since there
  is no way to justify the 1 on i

1
D
D
D
D
1
0
D
1
1
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Path Sensitization Method Circuit Example

• Try simultaneous paths f h k L and
• g i j k L blocked at k because
  D-frontier (chain of D or D) disappears

1
D
D
1
1
D
D
D
1
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Path Sensitization Method Circuit Example

• Final try path g i j k L test found!

0
0
D
D
1
D
D
D
1
1
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D-Algorithm Top Level

1. Number all circuit lines in increasing level
   order from PIs to POs
2. Select a primitive D-cube of the fault to be the
   test cube
3. D-drive ()
4. Consistency ()
5. return ()

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D-Algorithm Propagation

• D-frontier all gates whose output is X, at least
  one input is D or D
• J-frontier all gates whose output is defined,
  but is not implied by the input values

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Example 7.2 Fault A sa0

• Step 1 D-Drive Set A 1

D
1
D
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Step 2 -- Example 7.2

• Step 2 D-Drive Set f 0

0
D
D
1
D
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Step 3 -- Example 7.2

• Step 3 D-Drive Set k 1

1
D
0
D
D
1
D
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Step 4 -- Example 7.2

• Step 4 Consistency Set g 1

1
1
D
0
D
D
1
D
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Step 5 -- Example 7.2

• Step 5 Consistency f 0 Already set

1
1
D
0
D
D
1
D
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Step 6 -- Example 7.2

• Step 6 Consistency Set c 0, Set e 0

1
1
0
D
0
0
D
D
1
D
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D-Chain Dies -- Example 7.2

• Step 7 Consistency Set B 0
• D-Chain dies

X
1
1
0
D
0
0
0
D
D
1
D

• Test cube A, B, C, D, e, f, g, h, k, L

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Example 7.3 Fault s sa1

• Primitive D-cube of Failure

1
D
sa1
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Example 7.3 Step 2 s sa1

• Propagation D-cube for v

1
D
1
sa1
D
0
D
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Example 7.3 Step 2 s sa1

• Forward Backward Implications

0
1
1
1
D
1
1
sa1
D
0
D
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Example 7.3 Step 3 s sa1

• Propagation D-cube for Z test found!

0
1
1
1
D
1
1
sa1
D
0
D
D
1
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PODEM High-Level Flow

1. Assign binary value to unassigned PI
2. Determine implications of all PIs
3. Test Generated? If so, done.
4. Test possible with more assigned PIs? If maybe,
   go to Step 1
5. Is there untried combination of values on
   assigned PIs? If not, exit untestable fault
6. Set untried combination of values on assigned PIs
   using objectives and backtrace. Then, go to Step
   2

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Example 7.3 -- Step 1 s sa1

• Select path s Y for fault propagation

sa1
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Example 7.3 -- Step 2 s sa1

• Initial objective Set r to 1 to sensitize fault

1
sa1
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Example 7.3 -- Step 3 s sa1

• Backtrace from r

1
sa1
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Example 7.3 -- Step 4 s sa1

• Set A 0 in implication stack

1
0
sa1
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Example 7.3 -- Step 5 s sa1

• Forward implications d 0, X 1

1
1
0
0
sa1
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Example 7.3 -- Step 6 s sa1

• Initial objective set r to 1

1
1
0
0
sa1
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Example 7.3 -- Step 7 s sa1

• Backtrace from r again

1
1
0
0
sa1
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Example 7.3 -- Step 8 s sa1

• Set B to 1. Implications in stack A 0, B 1

1
1
0
0
1
sa1
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Example 7.3 -- Step 9 s sa1

• Forward implications k 1, m 0, r 1, q 1,
  Y 1, s D, u D, v D, Z 1

1
1
0
0
0
1
sa1
D
1
1
1
D
D
1
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Backtrack -- Step 10 s sa1

• X-PATH-CHECK shows paths s Y and s u
  v Z blocked (D-frontier disappeared)

1
1
0
0
sa1
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Step 11 -- s sa1

• Set B 0 (alternate assignment)

1
0
0
sa1
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Backtrack -- s sa1

• Forward implications d 0, X 1, m 1, r 0,
• s 1, q 0, Y 1, v 0, Z 1. Fault not
  sensitized

1
0
0
0
1
1
0
sa1
1
0
1
0
1
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Step 13 -- s sa1

• Set A 1 (alternate assignment)

1
1
sa1
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Step 14 -- s sa1

• Backtrace from r again

1
1
sa1
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Step 15 -- s sa1

• Set B 0. Implications in stack A 1, B 0

1
1
0
sa1
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Backtrack -- s sa1

• Forward implications d 0, X 1, m 1, r 0.
  Conflict fault not sensitized. Backtrack

1
0
1
0
1
0
sa1
1
1
0
1
0
1
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Step 17 -- s sa1

• Set B 1 (alternate assignment)

1
1
1
sa1
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Fault Tested -- Step 18 s sa1

• Forward implications d 1, m 1, r 1, q
  0, s D, v D, X 0, Y D

0
1
1
1
1
D
1
sa1
D
0
D
D
X
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Comparison

• Path sensitization multiply SAT problems
• D-algorithm decisions are made at the J-frontier
• PODEM decisions are made at the PIs
• FAN
• Multiply paths are traced back simultaneously
• A decision can be made at a headline

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History of Algorithm Speedups
Algorithm D-ALG PODEM FAN TOPS SOCRATES Waicukaus
ki et al. EST TRAN Recursive learning Tafertshofer
et al.
Est. speedup over D-ALG (normalized to D-ALG
time) 1 7 23 292 1574 2189 8765
3005 485 25057
Year 1966 1981 1983 1987 1988 1990 1991 1993 1995
1997
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Sequential Circuits State!

• Combinational circuit testing is relatively easy
• Sequential circuit testing needs to drive
  sequential elements to specific state to test a
  fault

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Sequential Circuit Controllability and
Observability
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Ad-hoc Test
Inserting multiplexer improves testability
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Scan-based Test
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Scan-based Test Operation
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Scan-Path Testing
Partial-Scan can be more effective for pipelined
datapaths
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Boundary Scan (JTAG)
Board testing becomes as problematic as chip
testing
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Self-test
Rapidly becoming more important with
increasing chip-complexity and larger modules
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Design verification testing
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Production testing
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Cost of finding failing chip
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Thanks