Cu Damascene 101

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Copper Damascene Plating 1/5/06 Brandon
Brooks Process Development Engineer
Semitool Confidential
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• Outline
• Why Cu Interconnects?
• Damascene Process Flow
• Parameters Affecting Cu Interconnects
• Backside Clean and Bevel Etch

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Damascene Plating?
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Why Cu Interconnects?
Interconnect Metal Properties
Al Cu W
Melting Pt (C) 660 1,083 3,410
Oxidation in Air Rapid Self-Sealing Slow Not Self-Sealing Inert
Resistivity (mW-cm)
Crystalline 2.82 1.77 5.6
As Deposited 3.0-3.3 1.8-2.0 8-11
Self-Diffusion Coefficient (cm2s-1) _at_ 100 C 2.110-20 2.110-30
Coefficient of Thermal Expansion (Unit/C) 2410-6 1710-6 4.310-6
Alloy (Si, Cu)
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Why Cu Interconnects?
Interconnect Metal Properties
Al Cu Ag
Etch Properties Cl Br Plasmas Cl Br Plasmas F Cl Plasmas
Etch Rate (Å/min) 5,000 500 5,000

• Cu has a very slow etch rate
• Cu halides are solid at normal temperatures
• Changing from Al to Cu interconnects requires new
  process flow
• Enter Damascene plating

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Damascene Process Flow

• Typical Damascene Process Flow
• Dielectric Deposition
• Photoresist Deposition
• UV Exposure
• Develop Photoresist
• Etch Dielectric
• Remove Photoresist
• Barrier Deposition
• Seed Layer Deposition
• Electrochemical Deposition (ECD)
• Backside Clean and Bevel Etch
• Anneal
• Chemical Mechanical Polish (CMP)
• Repeat Steps 1-10 for Every Metal Layer

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Damascene Process Flow
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Copper Interconnect Parameters

• Key Factors Affecting Cu Interconnect Performance
• Gap-Fill
• CD Uniformity
• Overburden
• Anneal

AMDs 9 Cu Levels
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Copper Interconnect Parameters Gap-Fill

• Key Parameters for Gap-Fill
• Seed and Barrier Layers
• Uniformity
• Thickness
• Plating Recipe
• Hot Start (Initiation)
• Fill Current Density
• Waveform
• Plating Chemistry
• Inorganic
• Organic

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Copper Interconnect Parameters Gap-Fill
Seed and Barrier Layers
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Copper Interconnect Parameters Gap-Fill
Seed and Barrier Layer Uniformity
Edge Shadowing
Optimized Seed Layer
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Copper Interconnect Parameters Gap-Fill
Seed and Barrier Layer Thickness
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Copper Interconnect Parameters Gap-Fill
Plating Recipe Hot Start
0.180 ?m Line Width Trenches 48 Coulombs ECD
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Copper Interconnect Parameters Gap-Fill
Plating Recipe Current Density
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Copper Interconnect Parameters Gap-Fill
Plating Recipe Waveform
Waveform Cu Diffusion Additive Adsorption Bottom Up Fill
Direct Current (DC) - 0
Pulse DC - 0
Pulse Reverse (PR) - 0
DC plating provides better additive
adsorption Pulsed plating provides better Cu
diffusion
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Copper Interconnect Parameters Gap-Fill
Plating Chemistry

• Inorganic Components
• Copper Sulfate (CuSO4)
• Hydrochloric Acid (HCl)
• Sulfuric Acid (H2SO4)

• Organic Components
• Suppressor (PEG)
• Accelerator (SPS)
• Leveler (Amine)

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Copper Interconnect Parameters Gap-Fill
Inorganic Plating Chemistry
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Copper Interconnect Parameters Gap-Fill
Inorganic Plating Chemistry
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Copper Interconnect Parameters Gap-Fill
Inorganic Plating Chemistry
pH 2
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Copper Interconnect Parameters Gap-Fill
Organic Plating Chemistry
Organic Effect on Gap Fill

• Accelerator
• Catalytic effect
• Requires very small amount of Cl-
• Increased current for a given potential
• Suppressor
• Suppresses deposition
• Requires Cl- to adsorb onto copper surface
• Decreases current for a given potential
• Leveler
• Suppresses deposition at high current density
  areas
• Very low concentration (diffusion limited)

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Copper Interconnect Parameters Gap-Fill
Organic Plating Chemistry
Cyclic Voltammetric Stripping Analysis (CVS)
A VMS B VMS Suppressor C VMS Sup.
Accel.
I
V
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Copper Interconnect Parameters Gap-Fill
Organic Plating Chemistry
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Copper Interconnect Parameters Gap-Fill
Organic Plating Chemistry
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Copper Interconnect Parameters Gap-Fill
Organic Plating Chemistry
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Copper Interconnect Parameters Gap-Fill
Organic Plating Chemistry
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Copper Interconnect Parameters Gap-Fill
Organic Plating Chemistry
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Copper Interconnect Parameters Gap-Fill
Organic Plating Chemistry
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Copper Interconnect Parameters Gap-Fill
Organic Plating Chemistry
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Copper Interconnect Parameters CD Uniformity

• Key Parameters for Current Density Uniformity
• Chemistry
• High Acid
• Low Acid
• CFD Reactor
• Electric Field Control

Intel 8 Cu Levels
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Copper Interconnect Parameters CD Uniformity
Generalized Electrochemical Schematic
Electrolytic Copper Deposition
Ammeter
V0

Current Density Current
Surf. Area
Current Path
Electrolyte
Surface Area
Cu22e- ? Cu0
Cu0 ? Cu22e-
Cathode (Reduction)
Anode (Oxidation)
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Copper Interconnect Parameters CD Uniformity
Area
Surface Area
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Copper Interconnect Parameters CD Uniformity

• V
• Current Density
• Throughput
• Rcat
• Seed Layer Thickness
• Wafer Radius
• Relec
• Bath Conductivity

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Copper Interconnect Parameters CD Uniformity
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Copper Interconnect Parameters CD Uniformity
Terminal Effect
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Copper Interconnect Parameters CD Uniformity
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Copper Interconnect Parameters CD Uniformity
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Copper Interconnect Parameters CD Uniformity
Advanced Reactor Design Multiple Anodes Robust
system that can handle multiple
chemistries Built for the future with the
ability to handle shrinking die size Cost
effective ability to handle increasing wafer
diameters
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Copper Interconnect Parameters CD Uniformity
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Copper Interconnect Parameters CD Uniformity
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Copper Interconnect Parameters CD Uniformity
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Copper Interconnect Parameters CD Uniformity
100 nm Seed layer, 1?m deposition
SEMITOOL - CFD
Conventional
High Acid 511mS/cm
Low Acid 70mS/cm
Wafer Radius (mm)
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Copper Interconnect Parameters CD Uniformity
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Copper Interconnect Parameters Overburden

• Key Parameters for Overburden
• Local Overburden (Overplating) Fill Step
• Chemistry
• 3-Component
• 2-Component
• Waveform
• Direct Current
• Pulse Reverse
• Global Overburden Cap Step
• Chemistry
• High Acid
• Low Acid
• CFD Reactor

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Copper Interconnect Parameters Local Overburden
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Copper Interconnect Parameters Local Overburden
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Copper Interconnect Parameters Global Overburden
Cu Thickness (Å)
Wafer Diameter (mm)
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Copper Interconnect Parameters Global Overburden
Raider CFD Profile Before After 30s CMP
16,000
12,000
CFD Profile before CMP
Thickness (A)
8,000
Uniform Post-CMP Profile
Profile after 30s CMP
4,000
POR Profile Before After 30s CMP
16,000
POR Profile before CMP
12,000
Thickness (A)
Early Clearing!
8,000
Profile after 30s CMP
Edge Residual!
4,000
Wafer Diameter
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Copper Interconnect Parameters Global Overburden
CMP Profile Matching
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Copper Interconnect Parameters Anneal

• Key Parameters for Anneal
• Temperature
• Feature Size
• Barrier Layer

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Copper Interconnect Parameters Anneal
Effect of Temperature
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Copper Interconnect Parameters Anneal
Effect of Feature Size
1.0?m Trenches
0.25?m Trenches
Furnace Anneal
Self-Anneal
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Copper Interconnect Parameters Anneal
Effect of Barrier Layer
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Copper Interconnect Parameters Anneal
Optimum Anneal Condition
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Backside Clean and Bevel Etch

• Why Backside Clean and Bevel Etch?
• Cu is a highly mobile ion
• Backside contamination can have adverse effects
  across the fab
• Unstable films on the edge of the wafer can cause
  surface damage at CMP

• Objective
• Remove bulk Cu on the edge of the wafer
• Delamination
• Flaking
• Yield Problems
• Remove atomic Cu on the back of the wafer
• Common Photolithography
• Common Metrology
• Cu ion diffusion

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Capsule 1 Chamber Cut Away
Backside Clean and Bevel Etch

• Capsule 1 Features
• Hardware control of bevel etch (BE)
• 0-4mm BE edge exclusion (EE) range
• No front side protection needed
• BE backside clean simultaneously
• Clean N2 purged microenvironment

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Backside Clean and Bevel Etch
Capsule Dynamics
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Backside Clean and Bevel Etch
Capsule Dynamics
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Backside Clean and Bevel Etch
Precision Control of Chemical Wrap-Around
A concentric 1.5mm EE BE clears the notch

• Critical Bevel Etch Parameters
• Concentricity
• Complete Cu Clearing
• Clearing the Notch

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Backside Clean and Bevel Etch
Precision Control of Concentricity
Concentricity Spec (a) 0.2mm
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Backside Clean and Bevel Etch
Precision Control of Copper Removal
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Summary

• Why Cu Interconnects?
• Resistivity
• Reliability
• Damascene Process Flow
• Photolithography to CMP
• Parameters Affecting Cu Interconnects
• Gap-Fill
• Current Density Uniformity
• Overburden
• Anneal
• Backside Clean and Bevel Etch
• Bulk Cu on the Edge
• Atomic Cu on the Backside

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Acknowledgements John Klocke Cu Damascene
Group Leader Kevin Witt Cu Damascene Business
Development Leader Tom Ritzdorf Director of ECD
Technology Jake Cook Marketing
Communications All Semitool personnel that have
contributed data to this presentation