CMOS Layers

1
CMOS Layers

• n-well process
• p-well process
• Twin-tub process

2
n-well process
MOSFET Layers in an n-well process
3
Layer Types

• p-substrate
• n-well
• n
• p
• Gate oxide
• Gate (polycilicon)
• Field Oxide
• Insulated glass
• Provide electrical isolation

4
Top view of the FET pattern
PMOS
NMOS
NMOS
PMOS
n-well
5
Metal Interconnect Layers

• Metal layers are electrically isolated from each
  other
• Electrical contact between adjacent conducting
  layers requires contact cuts and vias

6
Metal Interconnect Layers
Ox3
Via
Metal2
Active contact
Ox2
Metal1
Ox1
p-substrate
n
n
n
n
7
CMOS Gate Design

• A 4-input CMOS NOR gate

8
Complementary CMOS

• Complementary CMOS logic gates
• nMOS pull-down network
• pMOS pull-up network
• a.k.a. static CMOS

9
Series and Parallel

• nMOS 1 ON
• pMOS 0 ON
• Series both must be ON
• Parallel either can be ON

10
Conduction Complement

• Complementary CMOS gates always produce 0 or 1
• Ex NAND gate
• Series nMOS Y0 when both inputs are 1
• Thus Y1 when either input is 0
• Requires parallel pMOS
• Rule of Conduction Complements
• Pull-up network is complement of pull-down
• Parallel -gt series, series -gt parallel

11
Compound Gates

• Compound gates can do any inverting function
• Ex AND-AND-OR-INV (AOI22)

12
Example O3AI

13
Example O3AI

14
Pass Transistors

• Transistors can be used as switches

15
Pass Transistors

• Transistors can be used as switches

16
Signal Strength

• Strength of signal
• How close it approximates ideal voltage source
• VDD and GND rails are strongest 1 and 0
• nMOS pass strong 0
• But degraded or weak 1
• pMOS pass strong 1
• But degraded or weak 0
• Thus NMOS are best for pull-down network
• Thus PMOS are best for pull-up network

17
Transmission Gates

• Pass transistors produce degraded outputs
• Transmission gates pass both 0 and 1 well

18
Transmission Gates

• Pass transistors produce degraded outputs
• Transmission gates pass both 0 and 1 well

19
Tristates

• Tristate buffer produces Z when not enabled

20
Nonrestoring Tristate

• Transmission gate acts as tristate buffer
• Only two transistors
• But nonrestoring
• Noise on A is passed on to Y (after several
  stages, the noise may degrade the signal beyond
  recognition)

21
Tristate Inverter

• Tristate inverter produces restored output
• Note however that the Tristate buffer
• ignores the conduction complement rule because we
  want a Z output

22
Tristate Inverter

• Tristate inverter produces restored output
• Note however that the Tristate buffer
• ignores the conduction complement rule because we
  want a Z output

23
Multiplexers

• 21 multiplexer chooses between two inputs

24
Multiplexers

• 21 multiplexer chooses between two inputs

25
Gate-Level Mux Design

• How many transistors are needed?

26
Gate-Level Mux Design

• How many transistors are needed? 20

27
Transmission Gate Mux

• Nonrestoring mux uses two transmission gates

28
Transmission Gate Mux

• Nonrestoring mux uses two transmission gates
• Only 4 transistors

29
Inverting Mux

• Inverting multiplexer
• Use compound AOI22
• Or pair of tristate inverters
• Essentially the same thing
• Noninverting multiplexer adds an inverter

30
41 Multiplexer

• 41 mux chooses one of 4 inputs using two selects

31
41 Multiplexer

• 41 mux chooses one of 4 inputs using two selects
• Two levels of 21 muxes
• Or four tristates

32
D Latch

• When CLK 1, latch is transparent
• Q follows D (a buffer with a Delay)
• When CLK 0, the latch is opaque
• Q holds its last value independent of D
• a.k.a. transparent latch or level-sensitive latch

33
D Latch Design

• Multiplexer chooses D or old Q

Old Q
34
D Latch Operation
35
D Flip-flop

• When CLK rises, D is copied to Q
• At all other times, Q holds its value
• a.k.a. positive edge-triggered flip-flop,
  master-slave flip-flop

36
D Flip-flop Design

• Built from master and slave D latches

A negative level-sensitive latch
A positive level-sensitive latch
37
D Flip-flop Operation
Inverted version of D
Holds the last value of NOT(D)
Q -gt NOT(NOT(QM))
38
Race Condition

• Back-to-back flops can malfunction from clock
  skew
• Second flip-flop fires Early
• Sees first flip-flop change and captures its
  result
• Called hold-time failure or race condition

39
Nonoverlapping Clocks

• Nonoverlapping clocks can prevent races
• As long as nonoverlap exceeds clock skew
• Good for safe design
• Industry manages skew more carefully instead

40
Gate Layout

• Layout can be very time consuming
• Design gates to fit together nicely
• Build a library of standard cells
• Must follow a technology rule
• Standard cell design methodology
• VDD and GND should abut (standard height)
• Adjacent gates should satisfy design rules
• nMOS at bottom and pMOS at top
• All gates include well and substrate contacts

41
Example Inverter
42
Layout using Electric
Inverter, contd..
43
Example NAND3

• Horizontal N-diffusion and p-diffusion strips
• Vertical polysilicon gates
• Metal1 VDD rail at top
• Metal1 GND rail at bottom
• 32 ? by 40 ?

44
NAND3 (using Electric), contd.
45
Interconnect Layout Example
Gate contact
Metal1
Metal2
Metal1
MOS
Active contact
46
Designing MOS Arrays
A
B
C
y
x
B
C
A
y
x
47
Parallel Connected MOS Patterning
x
x
A
B
A
B
X
X
X
y
y
48
Alternate Layout Strategy
x
x
X
X
A
B
B
A
X
X
y
y
49
Basic Gate Design

• Both the power supply and ground are routed using
  the Metal layer
• n and p regions are denoted using the same fill
  pattern. The only difference is the n-well
• Contacts are needed from Metal to n or p

50
The CMOS NOT Gate
Contact Cut
Vp
Vp
X
n-well
X
X
X
Gnd
Gnd
51
Alternate Layout of NOT Gate
Vp
Vp
X
X
X
X
Gnd
Gnd
52
NAND2 Layout
Vp
X
X
X
X
X
Gnd
53
NOR2 Layout
Vp
X
X
X
X
X
Gnd
54
NAND2-NOR2 Comparison
MOS Layout
Wiring
55
General Layout Geometry
Vp
Shared drain/ source
Individual Transistors
Shared Gates
Gnd
56
Graph Theory Euler Path
Vp
x
Vertex
b
c
x
a
Edge
Out
y
c
y
Vertex
a
b
Gnd
57
Stick Diagram
58
Stick Diagrams

• Cartoon of a layout.
• Shows all components.
• Does not show exact placement, transistor
  sizes, wire lengths, wire widths, boundaries,
  or any other form of compliance with layout or
  design rules.
• Useful for interconnect visualization,
  preliminary layout layout compaction,
  power/ground routing, etc.

59
Stick Diagrams
60
Stick Diagrams
Buried Contact
Contact Cut
61
Stick Diagrams

• Stick diagrams help plan layout quickly
• Need not be to scale
• Draw with color pencils or dry-erase markers

62
Stick Diagrams

• Stick diagrams help plan layout quickly
• Need not be to scale
• Draw with color pencils or dry-erase markers

63
Wiring Tracks

• A wiring track is the space required for a wire
• 4 ? width, 4 ? spacing from neighbor 8 ? pitch
• Transistors also consume one wiring track

64
Well spacing

• Wells must surround transistors by 6 ?
• Implies 12 ? between opposite transistor flavors
• Leaves room for one wire track

65
Area Estimation

• Estimate area by counting wiring tracks
• Multiply by 8 to express in ?

66
5 V Dep Vout Enh 0V
5 v
Vin
67
Stick Diagram - Example I
68
Stick Diagram - Example II
Power
Out
A
C
B
Ground
69

• Points to Ponder
• be creative with layouts
• sketch designs first
• minimize junctions but avoid long poly runs
• have a floor plan plan for input, output, power
  and ground locations

70
The End