??????? ??? ?? VHDL? ??? ??

1
??????? ??? ?? VHDL? ??? ??
2002???????????

• "? ??? 2002?? ????????? ???? ??? ??? ??
  (KRF-2002-048-D00058)"
• " This work was supported by Korea Research
  Foundation Grant. (KRF-2002-048-D00058)"

2
?1? ????(process)?
? 4? VHDL? ????

• ? ????(process)?
• ? ??? ??(behavioral description)??, ???? ????
  ???
• ????? ??.
• ? ??? ? ??? ????? ??
• ? process? ??? ????
• ? ??? ????? ???? ??, ??? process??? ??? ??
• ?? 4.1 ?????? ???? ??
•         ????-_??? process (?? ??)
•                              ???
•                             begin
•                              ???
•                           end process ????_???

3
?1? ????(process)?
? 4? VHDL? ????

• ?? 4.1 2x1 ?????
•          1     entity mux21 is      
•          2           port(a, b, sel in bit
•          3                       y out bit)
•          4     end mux21
•          5     architecture sam of mux21 is
•          6       begin
•          7        mux_exam process(a,b,sel)
•          8         begin 
•          9            y lt a
•        10           if (sel'1') then y lt b
•        11           end if
•        12       end process mux_exam
•        13    end sam

(a) ???                      (b)
??? ?? 4.1 2x1MUX.
4
?1? ????(process)?
? 4? VHDL? ????

• ? ???(wait statement)
• ? ??? ?????? ?? ???? ?? ??
• ? ?????? ??? ?? ????, ???? ??? ?? ??? ??? ??
• ? ????? ?? ??, ????? ??? ?? ??? ????? ??
• ? ????? ?? ??, ???? ???? ????? ??? ??? ??
• ?? 4.2 ???
•         1  wait for 10ns      -- 10ns?? ??? ?,
  ?? ?? ??
•         2  wait until clk'1'  -- clk? ??? ?? ?,
  ?? ?? ??
•         3  wait on a, b       -- a, b??? ???
  ??? ?? ?? ??
•         4  wait               -- ??? ??
• ?? 4.3 ???? ???
•        1  wait on a, b until clk '1'  
  -- a, b? ??? ??, clk? 1? ? ??? ??
•        2  wait on a, b until clk '1' for 10ns
  -- a, b? ??? ??, clk? 1 ? ? ??? ???? 10ns? ??
• ?? 4.4 ???? ??
•        1  architecture sam of and2 is
•        2     begin
•        3       process            -- ????? ?????
  ?? ??
•        4         begin
•        5          wait on a, b   -- ???? ??

5
?1? ????(process)?
? 4? VHDL? ????

• ? ???(conditional statement)
• if?, case?, loop?, exit?, next?, null?,
  return?
• ? if?(if statement)
•     ?? 4.2 if?? ??
•       ? ??? if?
•            if (??) then         --  (??)? ???
•               ??1            --  ??1?
  ??
•              else                -- ???
  ???
•               ??2            -- ??2? ??
  
•            end if
•       ? ?? if ?
•            if (??1) then         -- (??1)? ???
•                ??1            -- ??1? ??
  
•            elsif (??2) then    -- (??1)? ????
  (??2)? ???
•                ??2            -- ??2? ??
  
•                   ..
•            else                    -- ??? ??
  ???
•                ?? n           -- ?? n?
  ??    
•            end if                    

6
?1? ????(process)?
? 4? VHDL? ????

• ?? 4.5 ??? if?? ??
•           
• ltVHDL ??gt
•            1    architecture sam1 of MUX_unit is
•            2        begin
•            3          process (a, b,
  c)             --????? a,b,c? process? ??
•            4            begin
•            5                if ( c 1 )
  then        --?? MUX? c? ???
•            6                         y lt a and
  b   -- a and b? y? ??
•            7                   else               
     -- ?? c? ?? ???
•            8                         y lt a or
  b    -- a or b? y? ??
•            9                end if

?? 4.2 if?? MUX????
7
?1? ????(process)?
? 4? VHDL? ????

• ?? 4.6 ?? if?? ??
•            ltVHDL ??gt
•            1   architecture sam2 of MUX_unit is
•            2          begin
•            3            process (a, b, s0,
  s1)      -- ????? a,b,s0,s1? process??
•            4              begin
•            5                if ( s1 '1' )
  then         -- MUX? ???? s1? ???,
•            6                          y lt a and
  b     -- a and b? ?? y? ??
•            7                elsif ( s0 '1' )
  then    -- s1? ?? ???, s0? ???,
•            8                          y lt a or
  b       -- a or b? ?? y? ??
•            9                else                  
         -- ?? ? ??? ?? ???,
•            10                         y lt a xor
  b     -- a xor b? ?? y? ??
•            11                end if

?? 4.3 ?? if?? MUX????
8
?1? ????(process)?
? 4? VHDL? ????

• ?? 4.7 else ?? if?? ?? ?
•            ltVHDL ??gt
•          1  architecture sam3 of MUX_unit is
•          2      begin
•          3          process (clk)         
  -- clk? ??? ?? ?, process? ??
•          4              begin
•          5                 if clk'event and
  clk'1' then  -- event??? ???,
•          6                     q lt
  d               -- d? q? ??
•          7                 end if                
    -- else?? ???? ????
•          8          end process
•          9   end sam3

?? 4.4 D flip-flop? MUX????
9
?1? ????(process)?
? 4? VHDL? ????

• ? case?(case statement)
• ?? ?? ?? ??? ???? ???, ?? ?? ???, ??? ??
• ???? ??
• ?? 4.8 case?? ??
•    ltVHDL ??gt
•    1 case sel is               -- sel?? ????
•    2     when "00" gt       -- sel?? 00??
•    3          y lt d(0)        -- y lt d(0) ???
  ????
•    4     when "01" gt       -- sel?? 01??
•    5          y lt d(1)        -- y lt d(1) ???
  ????
•    6     when "10" gt       -- sel?? 10??
•    7          y lt d(2)        -- y lt d(2) ???
  ????
•    8     when others gt  -- sel?? ????
•    9          y lt d(3)        -- y lt d(3) ???
  ?? 
•   10 end case 

?? 4.5 case?? MUX ????
10
?1? ????(process)?
? 4? VHDL? ????

• ?? 4.9 case?? ??? ?????? ??
•       ltVHDL ??gt
•   1   architecture sam4 of MUX_ca is
•   2    begin
•   3     process (s, a, b)                  
  --????? s, a, b? process??
•   4       begin
•   5        case s is                        --
  case? ??
•   6         when "00" gt y lt a nor b   -- ???
  00?? a nor b? y? ??
•   7         when "01" gt y lt a nand b -- ???
  01?? a nand b? y? ??
•   8         when "10" gt y lt a xor b    -- ???
  10?? a xor b? y? ??
•   9         when others gt y lt a and b -- ??
  ???? a and b? y? ??
•   10       end case

?? 4.6 case? ??? MUX ????
11
?1? ????(process)?
? 4? VHDL? ????

• ? loop?(loop statement)
• ?? ??? ??? ??? ???? ??? ???
• ? ?? forloop?, whileloop?, loop?
• ?? 4.3 loop?? ??
•       ? forloop?
•         ??? for (????) in (????) loop
•                        ?????          --
  (???? downto ?? to) ?? ?? ??
•          end loop ???
•       ? whileloop?
•         ??? while (??) loop
•                     ?????           --
  (??)? ?? ??? ?? ??
•          end loop ???
•       ? ?? loop?
•         ???   loop
•                      ?????           -- ??
  ?? ??, loop? ??? ??
•          end loop ???         --
  exit?? ??

12
?1? ????(process)?
? 4? VHDL? ????

• ?? 4.10 forloop?? ??? decoder? ??          
•      ltVHDL??gt
•      1   architecture sam5 of decoder is
•      2   begin
•      3      process ( a )                -- ????
  a? ???? ??
•      4      begin
•      5  loop1 for k in 3 downto 0 loop
  -- ??? k,????
•      6                y(k) lt (a k)
  -- (3 downto 0)?? ??
•      7        end loop loop1
  
•      8     end process
•      9   end sam5

?? 4.7 decoder ? ???
13
?1? ????(process)?
? 4? VHDL? ????

• ?? 4.11 whileloop?? ?? ?
•    1 loop2 while s lt 20 loop    -- "s lt 20"
  s? 20?? ??? ??? ??
•    2          s s1 t ts  -- s?? 1? ???
  s? ?? ??, st??t? ??
•    3         end loop loop2

14
?1? ????(process)?
? 4? VHDL? ????

• ? ?? ??? exit?, next?, null?
• exit?/next? loop?? ??? ???? ?? ??
• null? ??? ?? ?? ?? ???? ???? ?? ??
• ?? 4.4 ?? ???? ??
•         exit  ??? when (??)     -- ??? ??? ??
  ???? loop? ????
•         next ??? when (??)     -- ??? ??? ??
  loop? ??? ??
•         null                           
  -- ??? ??? ?? ??
• ?? 4.12 forloop? ? exit?? ?? 
•      ltVHDL ??gt
•       1   process (rst)
•       2   begin
•       3       if rst '1' then             
  -- reset 1?? forloop? ??
•       4  loop3for x in add downto 0 loop -- ??x,
  ????add downto 0? forloop?
•       5         if xgt40 then exit loop3
  -- x? 40 ???? if? ??, loop3? ????
•       6         else
•       7               mem(x) lt (others gt '0') 
  -- x? 40?? ??? ??
•       8         end if
•       9       end loop loop3

15
?1? ????(process)?
? 4? VHDL? ????

• ?? 4.13 forloop? ? exitwhen?? ?? 
•      ltVHDL ??gt
•       1    process (rst)
•       2      begin
•       3       if rst '1' then             
  -- reset 1?? forloop? ??
•       4   loop3for x in add downto 0 loop --??x,
  ????add downto 0? forloop?
•       5         exit loop3 when xgt40     
  -- x? 40 ???? loop3? ????    
•       6               mem(x) lt (others gt '0')
  -- x? 40 ???? ??
•       7       end loop loop3
•       8   end process
• ?? 4.14 forloop? ? next?? ?? 
•      ltVHDL ??gt
•       1    process (rst)
•       2      begin
•       3       if rst '1' then             
  -- reset 1?? forloop? ??
•       4  loop4 for x in 8 downto 0 loop --??x,
  ????8 downto 0? forloop?
•       5         if x5 then               
  -- x5??,
•       6                next             
  -- loop4? ?? ??, 5?, 6?? ?? ?  

16
?1? ????(process)?
? 4? VHDL? ????

• ?? 4.15 whileloop? ? next?? ??
•      ltVHDL ??gt
•       1    process (rst)
•       2       variable x integer
•       3     begin
•       4          x '0' 
•       5       if rst '1' then             
  -- reset 1?? forloop? ??
•       6  loop5 while x lt 9 loop         
  -- while ?? loop?
•       7         if x5 then               
  -- x5??,
•       8                next               
  -- loop5? ?? ??, 5?, 6?? ?? ?  
•       9              else
•       10               mem(x) lt (others gt
  '0') -- x5? ??? ??
•       11                x x 1     
•       12         end if
•       13        end loop loop5
•       14   end process     
• ?? 4.16 null ?
•        ltVHDL ??gt
•        1  case sel is

17
?1? ????(process)?
? 4? VHDL? ????

• ? return ?
• ??(function) ?? ????(procdeure) ? ?????? ???
  ?,
• ??? ???? ??? ? ??? ??
• ?? 4.17 return?? ??(boolean? bit? ??? ??
  ????)
•       ltVHDL ??gt
•        1    function bool_bit (a boolean)
  return bit is -- ??? ? x? bit?
•        2      begin                               
            -- ????? ?? ??   
•   3        if a then        -- a?? ???? ???
  
•        4             return '1'  -- ? 1? ????
  ??? ??
•        5        else             -- ?? ???
•        6             return '0'  -- 0? ????
  ??? ?
•        7        end if
•        8    end bool_bit

18
?1? ????(process)?
? 4? VHDL? ????

• ? ??? ????(multiple process)
• ??? ???? ?? ??? process?? ??
• ?? 4.18 process?? ????

?? 4.8 process? ????? ?? ????
19
?1? ????(process)?
? 4? VHDL? ????

• ltVHDL ??gt
•        1    architecture sample of logic is     
  -- process? process?? ????
•        2        signal w, x bit                
  -- w, x? ??? ??? ??? ??
•        3       begin                              
              
•        4     label1 process(a,
  b)                -- OR??? ??
•        5         begin
•        6         if(a'1')or(b'1') then wlt'1'
  -- process ??? ???, w lt a or b ?? ??
•        7         else    w lt '0'             
•        8         end if
•        9      end process
•        10   label2 process(b,
  c)                  -- NAND???
  ??                
•        11       begin                           
•        12        if (b'0')or(c'0') then x
  lt'1' -- process ??? ???, x lt b nand c ? ??
•        13        else   x lt '0'
•        14        end if
•        15       end process
•        16   label3 process(w,
  x)                 -- XOR??? ??               
  
•        17        begin                           
  
•        18          if (wx) then y lt'0' 
  -- process ??? ???, y lt w xor x? ??

20
?2? ??? ??(behavioral representation)
? 4? VHDL? ????

• ? ??? ????(behavioral description)
• ??? ???? ??? ????? ???? ??? ?????? ?????
• ?? ??
• ? ?????(concurrent statement)  
• ? ??? ???? ???? ??? ???? VHDL ??? ????? ??
• ?? 4.19 ????? ????
•     ltVHDL ??gt    
•      1    architecture sam1 of comb_logic is   
  -- sam2? ?? ???? ??
•      2      begin
•      3        c lt a and b        -- ???? ??????
  ??? ??
•      4        d lt a or b
•      5    end sam1
•      6  -- ???? ?? ???? ??
•      7    architecture sam2 of comb_logic is   
  -- sam1? ?? ???? ??
•      8      begin
•      9        d lt a or b         -- ???? ??????
  ??? ??

?? 4.9 ????? ????
21
?2? ??? ??(behavioral representation)
? 4? VHDL? ????

• ? ??? ??(signal assignment)
• ??? ??? lt ??? ??, lt? ????? ???? ??? ??
• ?????? ??? process? ??? signal? ??, ?????? ???
  
• ???? ? signal? ??
• ? ??(signal)? ???
•    ?? 4.20 ??? ???
•             w  lt  a         -- w? a? ??
  ?????? ??
•             x  lt  '0'        -- x? ?? 0??
  ??
•             y  lt  a and b  -- y? a and b"? ??
  ??
•            ?        ?
•      signal??   ?
• ? ???? ???
•    ?? 4.21 ???? ???
•        1     architecture con of assign is
•        2         signal in1, in2 bit  -- in1,
  in2? signal??? ??
•        3       begin
•        4         in1 lt a or b       -- in1?
  a or b"? ?? ??
•        5         in2 lt b or c      -- in2?
  b or c"? ?? ??
•        6         out lt in1 and in2  -- out? (a
  or b) and (b or c)"? ?? ??

22
?2? ??? ??(behavioral representation)
? 4? VHDL? ????

• ?? 4.22 2x1MUX? ?? ????? ????
•    ltVHDL??gt
•     1    architecture comb of mux21 is
•     2        signal nand1, nand2, inv1 bit  --
  nand1, nand2, inv1? signal? ??
•     3      begin
•     4         and1 lt a nand s       -- ????
  ???
•     5         and2 lt b nand inv1    -- ???? ???
  
•     6         inv1 lt not s            --
  ???? ???
•     7            z lt and1 nor and2  -- ???? ???
  
•     8     end comb

?? 4.10 2x1 MUX? ????
23
?2? ??? ??(behavioral representation)
? 4? VHDL? ????

• ? ?? ???? ???? delta??, ????, ????
• ? delta?? VHDL???? ???? ?? 0? ??? ????
• ? ???? ?? ?? ?????? ??? ??? ???? ?? ??
• ???? ??
• ? ???? ?? ??? ??? ?? ??? ?????? ?? ??
• ??? ??? ???? ???? ?? 
•      ?? 4.23 ?? ???? ????
•             b lt a                         --
  delta??
•             c lt transport a after 10ns  -- ????
  
•             d lt a after 10ns             --
  ????  

?? 4.11 ????? ??
24
?2? ??? ??(behavioral representation)
? 4? VHDL? ????

• ?? 4.24 ?? ?? ??
• ?? 4.25 ?? ?? ??

?? 4.12????? ???? ??
?? 4.13 ????? ???? ??
25
?2? ??? ??(behavioral representation)
? 4? VHDL? ????

• ? ??? ?? ?????(condional concurrent signal
  assignment)
• ? whenelse?
•    ?? 4.5 whenelse?? ??   
•        ??_?? lt ?1 when (??1) else
•                     ?2 when (??2) else
•              ????
•                      ?n-1 when (??n-1)
  else
•                     ?n
•    ?? 4.26 whenelse? ??   

?? 4.14 4x1MUX? ??
26
?2? ??? ??(behavioral representation)
? 4? VHDL? ????

• ltVHDL??gt
•       1     library ieee
•       2     use ieee.std_logic_1164.all
•       3     entity mux4_1 is
•       4       port ( d in std_logic_vector(3
  downto 0)  -- 4bit data??
•       5             sel in std_logic_vector(1
  downto 0)   -- 2bit ????
•       6              y out std_logic_vector(3
  downto 0))  -- 4bit data??
•       7     end mux4_1 
•       8     architecture sample of mux4_1 is
•       9       begin
•      10          y lt d(0) when sel "00" else
•      11                d(1) when sel "01" else
•      12                d(2) when sel "10" else
•      13                d(3)
•      14     end sample

27
?2? ??? ??(behavioral representation)
? 4? VHDL? ????

• ? ??? ?? ?????(selected concurrent signal
  assignment)
• ? withselect?
•      ?? 4.6 withselect?? ??   
•        ??_?? lt ?1 when ?? ???1
•                     ?2 when ?? ???2
•             ????
•                     ?n-1 when ?? ???n-1
•                     ?n  when others
•      ?? 4.27 withselect?? ??
•         ltVHDL ??gt    
•          1   with x select     
•          2       z lt "0001" when "00" 
•          3              "0010" when "01"
•          4              "0100" when "10"
•          5              "1000" when others

?? 4.15 2x4 decoder??
28
?3? ????? ??(dataflow description)
? 4? VHDL? ????

• ? ????? ??(data flow description)
• ???? ????? ??? ??, ??? ??? ??? ??? ??
• ??? ??? ???? ???? ???? ???? ??? ??,
• ????, ????? ? ?? ??? ????, ???? ?????
• ??
• ? ??????? ??
• ?? 4.28 ???? ??? ??(??? ???)
•   ltVHDL??gt
•    1     entity pari_check is
•    2        port ( a in std_logic_vector(4
  downto 0)
•    3              parity_checker out
  std_logic)
•    4     end pari_check
•    5     architecture data_flow of pari_check is
•    6        begin
•    7        parity_checker lt a(4) xor a(3) xor
  a(2) xor a(1) xor a(0)
•    8     end data_flow

?? 4.16 ??? ???
29
?4? ??? ??(structural description)
? 4? VHDL? ????

• ? ??? ??(structural description)
• ??? ??? ????? ??? ??? ?? ??? ??, ?? ???
• ??? ???? ?? ???? ??? ?? ???? ??
• ? ?? ???(direct instantiation)
•      ?? 4.7 ??? ??? ??
•           ??_?? entity work. ???_??(????_??)
•      ?? 4.29 ??? ???

?? 4.17 ??? ??? ?? ???
30
?4? ??? ??(structural description)
? 4? VHDL? ????

• ltVHDL ??gt
•         1    entity dlatch_en is           --
  ???? ????? ??
•         2        port(din, clk, en in bit
•         3                     qout out bit)
•         4    end dlatch_en
•         5    architecture structure of dlatch_en
  is
•         6       signal int_clk bit         --
  ?????? int_clk? ??
•         7      begin
•         8      gate entity work.and2(beh)       
     -- ?? AND??? and2 ???
•         9         port map (in1 gt clk, in2 gt
  en,  -- ?? and2 ?? ??     
•        10                   out1 gt
  int_clk)          -- ??? ???? ??
•        11      latch entity work.dlatch(beh)    
     -- ?? dlatch? ???
•        12         port map (d gt din, clk gt
  int_clk, -- ?? dlatch? ?? ??
•        13                    q gt
  qout)              -- ?? ??
•        14    end structure

31
?4? ??? ??(structural description)
? 4? VHDL? ????

• ? ?? ??(??)?(component instantiation)
• ? component?
•       ?? 4.8 component?? ?? ??
•           component ??_??
•              generic(???_???)   --
  ???(generic)
•              port(??_???)
•           end component
•       ?? 4.30 component?? ??
•        1   architecture structure of count is
•        2        component dff          -- ?? dff?
  ???
•        3           port (rst, clk, d in
  std_logic
•        4                         q out
  std_logic)
•        5        end component diff
•        6      begin ???

32
?4? ??? ??(structural description)
? 4? VHDL? ????

• ?? 4.9 ?? ???(component instantiation)
  ??
•            ??? ??_?? port map(??_???)
•                               generic
  map(??_???)
•           ???_??? ????, ????
•            ? ???? component? ??? ??? ????? ???
• port??? ??? ???? ??
•            ? ???? component? ??? ??? ????? ???
• ?? ???? ??

33
?4? ??? ??(structural description)
? 4? VHDL? ????

• ?? 4.31 component? ??? ?? ??? 
•   ltVHDL ??gt
•   1     entity nand_gate is
•    2        port(in1, in2, in3, in4 in
  std_logic
•    3                    out1, out2 out
  std_logic)
•    4     end nand_gate
•    5     architecture example of nand_gate is
•    6         component nand2  -- ????? begin?? ??
  nand2 ??
•    7             port (a, b in std_logic y
  out std_logic)
•    8         end component
•    9       begin
•  10       u1 nand2 port map (in1, in2, out1)  
  -- ??? ????
•  11       u2 nand2 port map (agtin3, bgtin4,
  ygtout2) -- ??? ????
•  12      end example

?? 4.18 NAND_gate
34
?4? ??? ??(structural description)
? 4? VHDL? ????

• ? ??(generate)?
• component? ????? ???? ???? ?? ??
• ?? 4.10 ??(generate)?? ??
•       ? ?? ?? ??
•      ??? for (??) in (????) generate
•                  ?????           --
  ?????? ???? ?? ??
•           end generate ??? 
•    ? ?? ?? ??                 
•     ??? if (??) generate   -- ??? ??? ? ??
  
•                  ?????
•           end generate ???

35
?4? ??? ??(structural description)
? 4? VHDL? ????

• ?? 4.32 ???? ???? ??
• ltVHDL??gt
• 1    architecture example of nand_system is
• 2        component nand2        
• 3           port (a, b in std_logic y out
  std_logic)
• 4        end component
• 5      begin
• 6       g1 for i 3 downto 0 generate      
  -- 4?? ????
• 7       ux nand2 port map (a(i), b(i), y(i)) 
  -- ?? ??             
• 8    end example

?? 4.19 nand_system
36
?4? ??? ??(structural description)
? 4? VHDL? ????

• ?? 4.33 ?? ?? ???? ??
•      ltVHDL ??gt
•    1    architecture example of xor_system is
•     2       signal y bit_vector(3 downto
  0)  -- ??? ??? ??? ??? ??
•     3      begin
•     4       g1 for i in 3 downto 0 generate   --
  4?? ????? ??,
•     5             g2 if i 3 generate          
  -- i3? ??? ???? u3? ?? 
•     6             u3 xor2 port map (x(i1),
  x(i), y(i))
•     7             end generate g2
•     8             g3 if i lt 3 generate      
  -- ilt3? ??? ???? ux? ?? 
•     9              ux xor2 port map (y(i1),
  x(i), y(i))
•    10              end generate g3
•    11        end generate g1

?? 4.20 parity_checker
37
?4? ??? ??(structural description)
? 4? VHDL? ????

• ? ???(generic)?
• entity? component? ?? ??, ????? entity? ????
  ??? ??? ?????
• ??? ????? ?? ??, ????? ???? ??? ??
• ? generic? ????? ??
•      ? ?? ??? ??? ?? ????? ??
•        ?? 4.34 ?? ??? ??? ?? ????? ??
•           1     entity and_gate is
•           2        generic(size integer 8)
•           3        port(x, y in
  std_logic_vector(size-1 downto 0)
•           4                z out
  std_logic_vector(size-1 downto 0)
•           5     end and_gate
•           6     architecture combi_logic of
  and_gate is
•           7        begin
•           8           z lt x and y
•           9     end combi_logic
• ?? 4.35 component?? ??? ????? ??
•          6     architecture combi_logic of
  and_gate is
•           7          component and_gate
•           8          generic(size integer)

38
?4? ??? ??(structural description)
? 4? VHDL? ????

• ? ????? ??? ?? ????? ??
•      ?? 4.36 ????? ??? ?? ?? ??? ??
•           1     entity nandx is
•           2        generic(size integer 8)
•           3       port(x in std_logic_vector(siz
  e-1 downto 0)
•           4             z out std_logic)
•           5     end nandx
•           6     architecture combi_logic of nandx
  is
•           7        begin
•           8            process(x)
•           9              variable temp bit
•         10                begin
•         11                 temp x(0)
•         12                 for i in 1 to size-1
  loop
•         13                   temp temp and
  x(i)
•         14                 end loop
•         15               z lt not (temp)
•         16              end process
•         17     end combi_logic

?? 4.21 nand gate
39
?4? ??? ??(structural description)
? 4? VHDL? ????

• ? ?? ??(configuration declaration)
• ??(component)? ?? entity? architecture? ????
  ?? ??
• ? ??? ???? ??
•    ?? 4.11 ?? ??? ??? ??
•          configuration configuration_?? of
  entity_?? is
•              for architecture_??
•               for ??? component_??
•               use entity library_??.entity_??(arch
  itecture_??)
•               for ??? component_??
•               use configuration
  library_??.configuration_??
•              end for
•          end configuration_??

40
?4? ??? ??(structural description)
? 4? VHDL? ????

• ? ??? ??
•   ?? 4.37 ??? ??(4_bit register)
•    1 configuration 4_register of test is -- ????
  test? 4_register ??? ??
•    2    for sample                 
  -- ???? sample??
•    3       for bit0 dff             
  -- bit0? dff?? ??? ??
•    4          use entity dflip_flop(delay)  --
  dff? ???? dflip_flop, 
•    5       end for                  
   -- ????? delay
•    6       for others dff   
       -- ??? bit1, bit2, bit3? ?? ????
•    7          use entity dflip_flop(delay)  
•    8       end for
•    9    end for
•  10  end 4_register

41
?4? ??? ??(structural description)
? 4? VHDL? ????

• ?? 4.38 ????? ?? component?
•         architecture example of test_component is
  
•               component and2         -- and2 ????
  component? ??
•                   port ( a, b in bit
•                            y out bit)
•               end component
•               component nor2          -- nor2
  ???? component? ??
•                   port ( a, b in bit
•                            y out bit)
•               end component
•               component config        -- JK
  flip_flop? component? ??
•                   port ( clk, i in bit
•                          j, k  out bit)
•               end component
•            begin
•            u1 and2 port map( d, e, j ) 
  -- and2 port map? ?????? ??
•            u2 nor2 port map( f, g, k )  
  -- nor2 port map? ?????? ??
•            u3 config port map( h, n, l, m )
  --JK flip_flop? ?????? ??
•         end example

42
?4? ??? ??(structural description)
? 4? VHDL? ????

• ?? 4.39 component?? ???? ??
•    1   configuration config_logic of test is
  --config_logic? ?? ??,??? test
•    2      for samp_logic            -- ??? test?
  ???? ??? samp_logic
•    3        for u1 and2             -- u1?
  component? and2 
•    4         use entity logic_lib.andx(samp_logic1
  ) -- library? logic_lib,
•    5        for u2 nor2                         
  -- ? ?? ???? andx
•    6         use entity work.nor2(samp_logic2)
•    7        for u3 comf
•    8         use configuration logic_lib.conf1
•    9      end for
• 10   end config_logic 

43
?4? ??? ??(structural description)
? 4? VHDL? ????

• ? ?? ??(configuration specification)
• ?? ????? ???? ? ??? ?? library ?? ????
• ????? ???? ?
• ? ?? ??? ??
•    ?? 4.12 ?? ??? ??? ??    
•          for ???_??? component_??
•             use entity library_??.
  entity_??(architecture_??)
•                        generic (??_???) port
  map(??_???)
• ? ???- ???? ??  
•    ?? 4.40 ???_???? ??
•      for all MUX use entity work.inst(inst_beh)
  
•      for c1, c2, c3 inv use entity
  work.invert(invert_body)
•      for others ALU use configuration
  combi.myALU
•        ? all ??? ???? ??? ???? ?? component?
  ?? ??? ?,
• ???? ?? ??? ??
•        ? c1, c2, c3 3?? ??? ?? ??? ????? ???
  ????? invert?
• ?? ???? ?? invert_body? ??
•        ? others ?? ???? ??? ???? ??? ?? ?????
  ??

44
?4? ??? ??(structural description)
? 4? VHDL? ????

• ?? 4.41 ???? ??? ?? AND_OR???
•          -- 2?? AND gate 
•           1     entity and2_gate is
•           2        port(a, b in bit c out
  bit)
•           3     end and2_gate
•           4     architecture combi_logic of
  and2_gate is
•           5        begin
•           6           c lt a and b
•           7     end combi_logic     
•          -- 2?? OR gate
•           1     entity or2_gate is
•           2       port(a, b in bit c out
  bit)
•           3     end or2_gate
•           4     architecture combi_logic of
  or2_gate is
•           5        begin
•           6           c lt a or b
•           7     end combi_logic

45
?4? ??? ??(structural description)
? 4? VHDL? ????

• ?? 4.42 ????? ??(AND_OR???)
•          -- AND_OR???? entity? architecture
•           1     entity AND_OR is
•           2        port(A, B, X in bit C out
  bit)
•           3     end AND_OR
•           4     architecture structural of AND_OR
  is     
•           5       signal temp bit
•          -- component ???
•           6     component and2_gate
•           7        port(A, B in bit C out
  bit)
•           8     end component
•           9     component or2_gate
•          10        port(A, B in bit C out
  bit)
•          11     end component
•         -- ?? ???
•          12   for AND_G AND2_gate use entity
  work.AND2_gate(combi_logic) -- AND_G
•          13         port map(A, B, C) 
•          14   for OR_G OR2_gate use entity
  work. OR2_gate(combi_logic)  -- OR_G
•          15         port map(A, B, C)

46
?5? ??? ?? ??(others statement description)
? 4? VHDL? ????

• ? assert?
• VHDL??? ????? ??? ?? ??? ?? ??? ???? ????
  ????, ???
• ??? ?? ??? ??, ????? ?????? ??? ??.
• ?? 4.13 assert?? ??
•        assert ??            -- ??? ?? ???
•          report "??? ??   -- ??? ??? ??
•          severity severity_??   -- severity_???
  ?? ????? ?? ?? ??
•        severity_level? ??note(??? ??),
  warning(??),error(??),failure(??? ??)
• ?? 4.43 assert?? ??
•            process(d, clk)
•              variable last_event_d,
  last_event_clk time
•             begin
•        -- check for hold time
•         1     if d'event then     
•         2       assert now 0ns or
  (now-last_event_clk) gt hold_time
•         3          report "hold time too short"
•         4          severity failure
•         5          last_event_d now
•         6     end if

47
?5? ??? ?? ??(others statement description)
? 4? VHDL? ????

• ? overloading
• VHDL?? ???? ???, ??(function), ????(procedure)
  ??
• ?? ??? ?? ??? ?? ? ?? ?, ?? ?? ????? ??
• ?? 4.44 ??? ??
•          function "OR"(a, b std_logic)
•          function "OR"(a, b bit)
•          function "OR"(a, b std_logic_vector)
• ? ??(block)?? ????(guarded signal)
• ???? architecture ?? VHDL??? ?? ?? ????? ???
• ??? block?? ???? ?
• ? ? ??? ??
•       ? VHDL?? ??? ??? ?? ?? ?? ??
•       ? ????? ???? ?? ??? ???? ?? ??
• ?? 4.14 ??(block)?? ??
•        ??? block(?? ??)
•                    ?? ??
•                   begin
•                    ???
•                 end block ???

48
?5? ??? ?? ??(others statement description)
? 4? VHDL? ????

• ?? 4.45 ??(block)?? ??(??? ??)
•         -- VHDL?? 1
•            y1 lt '1' after 10ns
•            label1 block
•            begin
•              y2 lt '1' after 20ns
•              y3 lt '0' after 30ns
•            end block label1
•         -- VHDL ??2
•             y1 lt '1' after 10ns
•             y2 lt '1' after 20ns
•             y3 lt '0' after 30ns
• ?? 4.46 ??(block)?? ??(?? ??)
•         1    architecture guard_exam of and2 is
•         2      begin
•         3       b1 block(enable '1')
•         4        begin
•         5          x lt guarded
•         6                '1' when a '1' and b
  '1' else '0'