Enumeration of Irredundant Circuit Structures

1
Enumeration of Irredundant Circuit Structures

• Alan Mishchenko
• Department of EECS
• UC Berkeley

2
Overview

• Logic synthesis is important and challenging task
• Boolean decomposition is a way to do logic
  synthesis
• Several algorithms - many heuristics
• Drawbacks
• Incomplete algorithms - suboptimal results
• Computationally expensive algorithms - high
  runtime
• Our goal is to overcome these drawbacks
• Perform exhaustive enumeration offline
• Use pre-computed results online, to get good QR
  and low runtime
• Practical discoveries
• The number of unique functions up to 16 inputs is
  not too high
• The number of unique decompositions of a function
  is not too high

2
3
Small Practical Functions

• Classifications of Boolean functions
• Random functions
• Special function classes
• Symmetric
• Unate
• etc
• Logic synthesis and technology mapping deal with
• Functions appearing in the designs
• Functions with small support (up to 16 variables)
• These functions are called small practical
  functions (SPFs)
• We will concentrate on SPFs and study their
  properties
• In particular, we will ask
• How many different SPFs exist?
• How many different irredundant logic structures
  they have?

4
DSD Structure

• DSD structure is a tree of nodes derived by
  applying DSD recursively until remaining nodes
  are not decomposable
• DSD is full if the resulting tree consists of
  only simple gates (AND/XOR/MUX)
• DSD is partial if the resulting tree has
  non-decomposable nodes (called prime nodes)
• DSD does not exist if the tree is composed of one
  node

Full DSD
Partial DSD
No DSD
f
f
a
b
a
b
c
d
e
f
c
d
e
a
b
c
d
e
5
Computing DSD

• The input is a Boolean function
• The output is a DSD structure
• The structure is unique up to several
  normalizations
• Selection of base functions (elementary gates)
• Placement of inverters
• Factoring of multi-input AND/XOR gates
• Ordering of fanins of AND/XOR gates
• Ordering of data inputs of MUXes
• NPN representative of prime nodes
• This computation is fast and reliable
• Originally implemented with BDDs (Bertacco et al)
• In a limited form, re-implemented with truth
  tables
• Detects about 95 of DSDs of cut functions
• To put DSD computation in perspective
• For 8-LUT mapping, it takes roughly the same time
  to
• to compute structural cuts
• to derive their truth tables
• to compute DSDs of the truth tables

F(a,b,c,d) ab cd
6
Pre-computing Non-Disjoint-Support Decompositions

• Enumerate bound sets while increasing size
• Enumerate shared sets while increasing size
• If the boundshared set is irredundant
• Add it to the computed set
• Boundshared set is redundant
• If a variable can be removed and the resulting
  set is decomposable
• Ex (abCD) is redundant if (abcD)
  or (abD) is a valid set

H
G
a
b
C
D
e
H
H
G
G
c
e
e
a
b
D
a
b
c
D
7
Example of Non-DS Decomposition Mapping 41 MUX
into two 4-LUTs
The complete set of support-reducing bound-sets
for Boolean function of 41 MUX Set 0 S
1 D 3 C 5 xAcd yxAbef Set 1 S 1
D 3 C 5 xBce yxaBdf Set 2 S 1 D
3 C 5 xAde yxAbcf Set 3 S 1 D
3 C 5 xBde yxaBcf Set 4 S 1 D 3
C 5 xAcf yxAbde Set 5 S 1 D 3 C
5 xBcf yxaBde Set 6 S 1 D 3 C
5 xBdf yxaBce Set 7 S 1 D 3 C 5
xAef yxAbcd Set 8 S 1 D 4 C 4
xaBcd yxBef Set 9 S 1 D 4 C 4
xAbce yxAdf Set 10 S 1 D 4 C 4
xAbdf yxAce Set 11 S 1 D 4 C 4
xaBef yxBcd Set 12 S 2 D 5 C 4
xABcde yxABf Set 13 S 2 D 5 C 4
xABcdf yxABe Set 14 S 2 D 5 C 4
xABcef yxABd Set 15 S 2 D 5 C 4
xABdef yxABc
8
Application to LUT Structure MappingMatching
6-input function with LUT structure 44
Case 2
Case 1
Case 3
f
f
a
b
c
d
e
f
a
b
c
d
e
a
b
c
d
e
f
f
H
H
H
G
G
G
a
b
c
D
e
f
a
b
C
d
e
a
b
c
D
e
9
Application to Standard Cell Mapping

• Enumerate decomposable bound sets
• For each bound set, enumerate NPN classes of G
  and H
• Use them as choice nodes
• Use choice nodes to improve quality of Boolean
  matching
• Property When non-disjoint-support decomposition
  is applied, there are exactly M 2((2k)-1)
  pairs of different NPN classes of
  decomposition/composition functions, G and H,
  where k is the number of shared variables

F
H
G
k M
0 1
1 2
2 8
3 128
4 32768
5 2147483648
10
Example of a Typical SPF
abc 01gt rt 000A115F abc 02gt print_dsd d F
0505003F(a,b,c,d,e) This 5-variable function has
10 decomposable variable sets Set 0 S 1
D 3 C 4 xabC yxCde 0
ltcbagt 011Ddecf 1
ltc!bagt 110Ddecf Set
1 S 1 D 3 C 4 xbCd yxaCe 0
!(!d!(cb)) lte(!c!a)!fgt 1
1Cbdc
3407aecf Set 2 S 1 D 3 C 4 xabE
yxcdE 0 lteabgt
0153cdef 1 lte!abgt
5103cdef Set 3 S 1 D 3 C
4 xacE yxbdE 0 !(!c!(ea))
01F3bdef 1
1Cace F103bdef Set 4 S
1 D 3 C 4 xbcE yxadE 0
(c!(!e!b)) (!flte!a!dgt) 1
38bce 5003adef Set
5 S 1 D 3 C 4 xbCe yxaCd 0
!(!e!(cb)) ltf(!c!a)!dgt
1 1Cbec
3503adcf Set 6 S 1 D 3 C 4 xadE
yxbcE 0 lteadgt
(!f!(c!(!e!b))) 1 lte!adgt
3007bcef Set 7 S 1 D 4 C
3 xabcE yxdE 0 FAC0abce
(!f!(!ed)) 1
05C0abce C1def Set 8 S
1 D 4 C 3 xaCde yxbC 0
lte!(!c!a)dgt (!f!(cb)) 1
03ACadec
43bcf Set 9 S 1 D 4 C 3 xbcdE
yxaE 0 CCF8bcde
(!f!(ea)) 1 33F8bcde
43aef
abc 01gt rt 000A115F abc 02gt pk Truth table
000a115f d e \ a b c 0 0 0 0 1 1
1 1 0 0 1 1 1 1 0 0 0
1 1 0 0 1 1 0 --------------
---------- 00 1 1 1 1 1 1
------------------------ 01
1 1 ---------------
--------- 11
------------------------ 10 1 1
---------------
---------
NOTATIONS !a is complementation NOT(a) (ab)
is AND(a,b) ab is XOR(a,b) ltabcgt is MUX(a,
b, c) ab !ac lttruth_tablegtabc is PRIME
node
11
Statistics of DSD Manager

• abc 01gt pub12_16.dsd dsd_ps
• Total number of objects 3567880
• Externally used objects 3060774
• Non-DSD objects (max 12) 479945
• Non-DSD structures 3220044
• Prime objects 1405170
• Memory used for objects 100.04 MB.
• Memory used for functions 238.01 MB.
• Memory used for hash table 40.83 MB.
• Memory used for bound sets 79.98 MB.
• Memory used for array 27.22 MB.
• 0 All 1
• 1 All 1
• 2 All 2
• 3 All 10
• 4 All 229
• 5 All 3823

This DSD manager was created using cut
enumeration applied to all MCNC, ISCAS, and ITC
benchmarks circuits (the total of about 835K AIG
nodes). This involved computing 16 priority
12-input cuts at each node. Binary file
pub12_16.dsd has size 177 MB. Gzipped
archive has size 42 MB. Reading it into ABC
takes 3 sec. Harvesting functions contained in
this DSD manager took 1 hour.
12
Typical DSD Structures
NOTATIONS !a is complementation NOT(a) (ab)
is AND(a,b) ab is XOR(a,b) ltabcgt is MUX(a,
b, c) ab !ac lttruth_tablegtabc is a PRIME
node with hexadecimal lttruth_tablegt
13
Support-Reducing Decompositions

• For each support size (S) of NPN classes of
  non-DSD-decomposable functions
• the columns are ranges of counts of irredundant
  decompositions
• the entries are percentages of functions in each
  range
• - the last two columns are the maximum and
  average decomposition counts

14
LUT Structure Mapping

• LUT LUT count
• Level LUT level count
• Time, s Runtime, in seconds
• The last two columns
• with online DSD computations
• with offline DSD computations (based on
  pre-computed data)

15
LUT Level Minimization
6-LUT mapping Standard mapping into 6-LUTs with
structural choices LUTB DSD-based LUT balancing
proposed in this work SOPBLUTB SOP balancing
followed by LUT balancing (ICCAD11) LMSLUTB
Lazy Mans Logic Synthesis followed by LUT
balancing (ICCAD12)
16
Conclusions

• Introduced Boolean decomposition
• Proposed exhaustive enumeration of decomposable
  sets
• Discussed applications to Boolean matching
• Experimented with benchmarks to find a 3x speedup
  in LUT structure mapping
• Future work will focus on
• Improving implementation
• Extending to standard cells
• Use in technology-independent synthesis

17
Abstract

• A new approach to Boolean decomposition and
  matching is proposed. It uses enumeration of all
  support-reducing decompositions of Boolean
  functions up to 16 inputs. The approach is
  implemented in a new framework that compactly
  stores multiple circuit structures. The method
  makes use of pre-computations performed offline,
  before the framework is started by the calling
  application. As a result, the runtime of the
  online computations is substantially reduced. For
  example, matching Boolean functions against an
  interconnected LUT structure during technology
  mapping is reduced to the extent that it no
  longer dominates the runtime of the mapper.
  Experimental results indicate that this work has
  promising applications in CAD tools for both
  FPGAs and standard cells.