Synthesizable VHDL LC-2

1
Introduction
Synthesizable VHDL LC-2 Created By Eric
Frohnhoefer Ron Feliciano Under the Direction
of Professor Frank Vahid
2
Introduction
Synthesizable LC-2 Model

• Introduction into VHDL (5 min)
• LC-2 overview (5 min)
• Demonstration of fetch cycle (15 min)
• Researching (5 min)
• Question and Answer (remaining time)

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Introduction into VHDL
What is VHDL??
VHDL (Very High Speed Integrated Circuit)
Hardware Description Language
What do we use VHDL for??
VHDL is a programming language used for
verification and synthesis of digital designs.
Features of VHDL

• High level language
• Allows for rapid development of digital designs
• Syntactically similar to C
• Various methods of hardware description
• High level system verification

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Introduction into VHDL
VHDL code
C code
if ( condition ) expression
if ( condition ) then expression end if
case ( variable ) is when condition gt
Expression end case
switch ( variable ) case condition
expression break
Operators comparison assignment lt
assignment / not equal
Operators assignment comparison !
not equal
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Introduction into VHDL
LC-2 ALU VHDL Code library IEEE use
IEEE.std_logic_1164.all use IEEE.std_logic_unsign
ed.all use IEEE.std_logic_arith.all --LC-2
ALU--------------------------------------- entity
LC2_ALU is port( A in std_logic_vector (15
downto 0) B in std_logic_vector (15
downto 0) S in std_logic_vector (1 downto
0) O out std_logic_vector (15 downto
0)) end LC2_ALU architecture bhv of LC2_ALU
is begin process(A, B, S) begin case S is
when "00" gt O lt AB when "01" gt
O lt A and B when "10" gt O lt A
when "11" gt O lt not A when others gt
null end case end process end bhv
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LC-2 Logic Components
Basic Logic Components
Register/Register Bank
IN En OUT
1 1 1
0 0 Z
1 0 Z
0 1 0
Arithmetic Logic Unit (ALU)
Sel(01) Sel(11) Out
0 0 A B
0 1 A and B
1 0 A
1 1 not A
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LC-2 Overview

• Instruction Cycle
• Fetch - Fetch next instruction from main memory
  as indicated by the Program Counter (PC)
• Decode - Decodes the instruction returned by the
  fetch cycle.
• Address Evaluation - Calculate address of data
  and load into Memory Address Register (MAR).
• Operand Fetch - Load data into Memory Data
  Register (MDR).
• Execute - Perform given operation.
• Store Result - Store result into memory.

• Addressing modes
• Immediate Mode (LEA) - DR PC159 _at_ pgoffset9
• Direct Mode (LD) - DR memPC159 _at_ pgoffset9
• Indirect Mode (LDI) - DR memmemPC159 _at_
  pgoffset9
• BaseOffset Mode (LDR) - DR memBaseR
  ZEXT(index6)

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LC-2 Fetch Cycle
PC_Gate lt 1 MAR_ld lt 1
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LC-2 Fetch Cycle contd
PC_gate lt 0 MAR_ld lt 0 Read_Write lt
1 MIO_enable lt 1
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LC-2 Fetch Cycle contd
MIO_enable lt 0 MDR_ld lt 1
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LC-2 Fetch Cycle contd
MDR_ld lt 0 MDR_gate lt 1 IR_ld lt 1 PC_mux
lt "00" PC_ld lt 1
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LC-2 Fetch Cycle contd
IR_ld lt 0 PC_ld lt 0 MDR_gate lt 0
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LC-2 Stats
Here are some of the statistics we obtained by
synthesizing the LC-2 model down to gate level,
using the Synopsys Design Compiler with medium
mapping effort. We left the ram_modules in
behavioral level code since they would normally
not be synthesized into logic but rather loaded
into a memory.
component I/O Ports Combinational Area (gates) Sequential Area (gates) Critical Path (ns) Max Clock speed (MHz) Synthesis Time (sec)
LC2_ctrl 55 577 545 1.31 763 52
LC2_alu 50 242 0 20.3 49 16
LC2_reg_bank 59 766 1504 1.37 730 33
LC2_all 2 2781 4886 20.3 49 190

• www.cs.ucr.edu/efrohnho
• www.cs.ucr.edu/rfelicia
• http//www.cs.ucr.edu/vahid/sproj/lc2/index.html

Erics Webpage
Rons Webpage
LC-2 Webpage
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Researching