ECE 491 - Senior Design I

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ECE 491 - Senior Design I

• Lecture 2 FPGAs Verilog (for Lab 1)
• Fall 2008
• Handout Structural Design with Verilog - read
  Sections 1-5

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
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Todays Outline

• Overview Electronic Design with FPGAs
• Basic FPGA Structure
• FPGA Tradeoffs
• The Spartan-3 FPGA
• The Spartan-3 Starter Kit Board
• Hardware Description Languages
• Quick Verilog Overview
• What to do in Lab 1

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FPGA Organization - Overview
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FPGA Organization (Simplified)
CLB
CLB
CLB
IOB
SB
SB
SB
CLB
CLB
CLB
IOB
SB
SB
SB
IOB
IOB
IOB
IOB - Input/Output Block
CLB - Configurable Logic Block
SB - Switch Block
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FPGA Tradeoffs

• Advantages
• Very low development cost
• Post-manufacturing changes possible
• Powerful functions in a small package
• Relatively inexpensive
• Disadvantages
• Inefficient - unused CLBs are still on device
• Much slower than ASICs, Custom ICs
• Higher power than ASICs, Custom ICs
• More expensive than ASICs, Custom ICs in volume

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Spartan-3 Organization
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Spartan 3 CLB Structure
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Spartan 3 Slice Structure
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Spartan-3 XC3S200 Details

• 24 X 20 480 CLBs
• 12 Block RAMs (18kbits ea.)
• 12 Multipliers (18bit X 18bit)
• Up to 173 User I/O pins

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Starter Kit Board - Overview
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Starter Kit - Block Diagram
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Hardware Description Languages

• Verilog
• Designed by one person at a startup company
• Syntax similar to C
• Favored by industrial designers
• IEEE Standard 1364 (-1995, -2001, -2005)
• VHDL
• Designed by committee for the Department of
  Defense
• Syntax similar to Pascal, ADA
• Favored by government labs, contractors
• IEEE Standard 1076 (-1987, -1993, -2000, -2002,
  -2004)

Well use Verilog!
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Verilog Overview

• Important Points About Verilog
• The module construct
• Combinational Logic
• Parameters
• Module Instantiation
• Sequential Logic
• Finite State Machines

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Key Point Verilog is for Hardware!

• Verilog code is not like software!
• Hardware is parallel
• Software is sequential
• Think hardware and write code that describes
  hardware
• Follow coding guidelines to avoid pitfalls

Zen Master Lin Chi Yi-Sen (note stick)source
http//thezenfrog.wordpress.com
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Verilog Hardware Constructs
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Important Points about Verilog (contd)

• Verilog is based on event-driven simulation
• Signal values change at specific time points
• Each model
• Activates in response to input events
• Creates output events to represent output changes

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Important Points about Verilog (contd)

• Verilog was designed as a simulation language
• Synthesis added as an afterthought
• Only a subset of the language supported for
  synthesis
• Synthesis must match simulated behavior
• Follow coding guidelines to avoid difficulties

Image source http//oldcarandtruckpictures.com/Am
phicar/
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Important Points about Verilog (contd)

• Our focus the synthesizable subset
• Structural Descriptions - module instantiations
• Behavioral Descriptions
• assign - continuous assignments
• always blocks
• But, well use simulation capabilities for
  verification
• initial blocks
• tasks (subroutines), system tasks, functions
• Delay operator

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Verilog module construct

• Key building block of language
• Interface - input and output ports
• Body - specifies contents of "black box"
• behavior - what it does
• structure - how it's built from module instances
  (submodules)
• Mixed behavior and structure (discouraged)

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First Example Full Adder

• module fulladder(a, b, cin, sum, cout)
• input a, b, cin
• output sum, cout
• assign sum a b cin
• assign cout a b a cin b cin
• endmodule

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Comments about First Example

• Module interface input and output ports
• Single bit
• Multiple bit - array syntax
• Module internals
• Internal connections (wire) and variables (reg)
• Continuous assignment statements - assign
• Concurrent statements - always
• Submodule instantiation (hierarchy)
• Digital values (0, 1, X, Z)

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Example 7-Segment Decoder Part 1

• module seven_seg(data, segments)
• input 30 data
• output 60 segments
• reg 60 segments
• // Output patterns abc_defg
• parameter BLANK 7'b111_1111
• parameter ZERO 7'b000_0001
• parameter ONE 7'b100_1111
• parameter TWO 7'b001_0010
• parameter THREE 7'b000_0110
• parameter FOUR 7'b100_1100
• parameter FIVE 7'b010_0100
• parameter SIX 7'b010_0000
• parameter SEVEN 7'b000_1111
• parameter EIGHT 7'b000_0000
• parameter NINE 7'b000_0100

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Example 7-Segment Decoder Part 2

• always _at_(data)
• case (data)
• 4'd0 segments ZERO
• 4'd1 segments ONE
• 4'd2 segments TWO
• 4'd3 segments THREE
• 4'd4 segments FOUR
• 4'd5 segments FIVE
• 4'd6 segments SIX
• 4'd7 segments SEVEN
• 4'd8 segments EIGHT
• 4'd9 segments NINE
• default segments BLANK
• endcase
• endmodule

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Example Module Instance in s3board

• module s3board( clk, pb_in, sw_in,
  digit_enable_out, segment_out,
• segment_dp_out, led_out, rxd_in, txd_out )
• input clk // 50MHz clock from
  board
• input 30 pb_in // active-high
  pushbuttons (BTN3-BTN0)
• input 70 sw_in // active-high
  slide switches (SW7-SW0)
• output 30 digit_enable_out // active-low
  enable for the four
• // 7-seg
  display units (AN3-AN0)
• output 60 segment_out // active-low
  segments a (6) - g (0) -
• // shared
  between the four displays
• output segment_dp_out // active-low
  segment decimal point -
• // shared
  between the four displays
• output 70 led_out // 8
  active-high LEDs (LD7-LD0)
• input rxd_in // RS-232 port data
  in
• output txd_out // RS-232 port data
  out
• assign segment_dp_out 1b1 // turn OFF
  decimal point
• seven_seg U_SSEG( .data(sw_in30),
  .segments(segment_dp_out) )
• endmodule // s3board

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Using the S3 Board with Verilog

• Top-level module file s3board.v
• Contains declarations for all input output pins
• Switches pushbuttons
• LEDs and 7-segment displays
• RS-232 port(s)
• Not used (currently) PS/2 port, VGA port
• Use as a starting point for your design
• Constraint file s3board.ucf
• Contains pin assignments for all inputs outputs
• Uncomment pins that youre going to use (remove
  )
• Download these files from Moodle

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S3 Board Seven-Segment Display

• Segment signals - active low
• Digit enables used to time multiplex digits

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Lab 1 Goals

• Learn about the Spartan-3 Starter Kit Board
• Review Combinational Logic Design with Verilog
• Learn about Basic FPGA Design with Verilog

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What to Do in Lab 1

• Download s3board.v and s3board.ucf
• Run ISE and create a new project
• Add s3board.v and s3board.ucf
• Add Verilog code for a 4-bit adder
• Add Verilog code for a 7-segment decoder with hex
  digits
• Connect slide switches to adder inputs
• Connect 7-segment decoder to adder output
• Connect 7-segment decoder to display LSB
• Compile, download, debug
• Create report upload to Moodle (see rubric)

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Lab 1 - Block Diagram