A Greatest Common Divisor (GCD) Processor

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A Greatest Common Divisor(GCD) Processor

• Lecture L10.3
• Sections 10.4, 10.5

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Euclids GCD algorithm
GCD(9,15) x 9 y 15 y 15 9 6 x 9 6
3 y 6 3 3 GCD(9,15) 3
1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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ALU
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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GCD
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MODULE GCDpath interface(clk,clr,PA3..PA0,PB3..
PB0,r0ld,r1ld,stld,wld,msel1..msel0,alusel2..a
lusel0 -gt C,Z,PC3..PC0,PD3..PD0,PE3..PE0
) TITLE 'Datapath for GCD' DECLARATIONS alu
interface(A3..A0,B3..B0, s2..s0 -gt
Y3..Y0,CF,OVF,ZF,NF) alu1 FUNCTIONAL_BLOCK
alu reg4bit interface(D3..D0,clr,clk,load
-gt Q3..Q0) R0 FUNCTIONAL_BLOCK reg4bit R1
FUNCTIONAL_BLOCK reg4bit status FUNCTIONAL_BLOCK
reg4bit W FUNCTIONAL_BLOCK reg4bit mux44
interface(A3..A0,B3..B0,C3..C0,D3..D0,s1.
.s0 -gt Z3..Z0) M1 FUNCTIONAL_BLOCK mux44
gcdpath.abl
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gcdpath.abl (cont.)
" INPUT PINS " clk PIN " clock clr PIN "
clear PA3..PA0 PIN PA PA3..PA0
PB3..PB0 PIN PB PB3..PB0
r0ld, r1ld, stld, wld PIN msel1..msel0
PIN msel msel1..msel0 alusel2..alusel0
PIN alusel alusel2..alusel0
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gcdpath.abl (cont.)
" OUTPUT PINS " C, Z PIN ISTYPE 'com' "
carry and zero flags
PC3..PC0 PIN ISTYPE 'com' " 4-bit R0
output PC PC3..PC0
PD3..PD0 PIN ISTYPE 'com' " 4-bit R1
output PD PD3..PD0
PE3..PE0 PIN ISTYPE 'com' " 4-bit W
output PE PE3..PE0
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gcdpath.abl (cont.)
EQUATIONS R0.load r0ld R0.clr clr R0.clk
clk R0.D3..D0 alu1.Y3..Y0 R1.load
r1ld R1.clr clr R1.clk clk R1.D3..D0
alu1.Y3..Y0 status.load stld status.clr
clr status.clk clk status.D3..D0
alu1.NF,ZF,OVF,CF
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gcdpath.abl (cont.)
W.load wld W.clr clr W.clk
clk W.D3..D0 alu1.Y3..Y0 M1.s1..s0
msel M1.D3..D0 R0.Q3..Q0 M1.C3..C0
R1.Q3..Q0 M1.B3..B0 PB M1.A3..A0
PA alu1.A3..A0 M1.Z3..Z0 alu1.B3..B0
W.Q3..Q0 alu1.s2..s0 alusel2..alusel0 C
status.Q0 Z status.Q2 PC R1.Q3..Q0 PD
R0.Q3..Q0 PE W.Q3..Q0 END GCDpath
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GCD
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1 int x, y 2 x x_input 3 y
y_input 4 while (x ! y) 5 6 if
(xlty) 7 y y-x 8 else 9 x
x-y 10 11 output x
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gcdctl.abl
MODULE gcdctl interface(Clk, Clear, Z, C -gt r0ld,
r1ld, stld, wld, msel1..msel0,
alusel2..alusel0, Q2..Q0) TITLE 'Control
Unit for GCD algorithm' DECLARATIONS " INPUT
PINS " Clk PIN " clock Z, C PIN " zero
and carry flags Clear PIN " clear " OUTPUT
PINS " r0ld, r1ld, stld, wld PIN " reg load
signals msel1..msel0 PIN " mux
selects alusel2..alusel0 PIN " alu select "
INTERMEDIATE NODES Q2..Q0 PIN ISTYPE 'reg
buffer' Q Q2..Q0 "
3-bit state vector
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gcdctl.abl (cont.)
" Definitions QSTATE Q2, Q1, Q0 s0 0, 0,
0 s1 0, 0, 1 s2 0, 1, 0 s3 0, 1,
1 s4 1, 0, 0 s5 1, 0, 1 s6 1, 1,
0 s7 1, 1, 1 state_diagram QSTATE state
s0 goto s1 state s1 goto s2 state
s2 goto s3 state s3 goto s4 state s4
if Z then s7 else if C then s5 else s6
state s5 goto s2 state s6 goto s2 state
s7 goto s7
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gcdctl.abl (cont.)
EQUATIONS WHEN QSTATE s0 then " R0 lt- x
r0ld 1 r1ld 0 stld 1 wld 0
msel1..msel0 0,0 alusel2..alusel0
0,0,0 WHEN QSTATE s1 then " R1 lt- Y
r0ld 0 r1ld 1 stld 1 wld 0
msel1..msel0 0,1 alusel2..alusel0
0,0,0
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gcdctl.abl (cont.)
WHEN QSTATE s2 then " W lt- R0 r0ld 0
r1ld 0 stld 1 wld 1 msel1..msel0
1,1 alusel2..alusel0 0,0,0 WHEN
QSTATE s3 then " W lt- R1 - W r0ld 0
r1ld 0 stld 1 wld 1 msel1..msel0
1,0 alusel2..alusel0 0,1,0
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gcdctl.abl (cont.)
WHEN QSTATE s4 then " W lt- R0 r0ld
0 r1ld 0 stld 1 wld 1
msel1..msel0 1,1 alusel2..alusel0
0,0,0 WHEN QSTATE s5 then " R0 lt- W
- R1 r0ld 1 r1ld 0 stld 1 wld 0
msel1..msel0 1,0 alusel2..alusel0
0,1,1
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gcdctl.abl (cont.)
WHEN QSTATE s6 then " R1 lt- R1 - W
r0ld 0 r1ld 1 stld 1 wld 0
msel1..msel0 1,0 alusel2..alusel0
0,1,0 WHEN QSTATE s7 then " DONE W
lt- R0 r0ld 0 r1ld 0 stld 1 wld
1 msel1..msel0 1,1
alusel2..alusel0 0,0,0 Q.C Clk Q.AR
Clear END
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GCD
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MODULE GCD TITLE 'Greatest Common
Divisor' DECLARATIONS " Functional Blocks
" gcdctl interface(Clk, Clear, Z, C -gt r0ld,
r1ld, stld, wld, m1sel, m2sel,
m3sel1..m3sel0, alusel2..alusel0) gcd1
FUNCTIONAL_BLOCK gcdctl GCDpath
interface(clk,clr,PA3..PA0,PB3..PB0,r0ld,r1ld,
stld,wld,m3sel1..m3sel0,m2sel,m1sel,alusel2.
.alusel0 -gt C,Z,PC3..PC0,PD3..PD0,PG3..
PG0) gcd2 FUNCTIONAL_BLOCK GCDpath hex7seg
INTERFACE(D3..D0 -gt a,b,c,d,e,f,g) d7R
FUNCTIONAL_BLOCK hex7seg
GCD.abl
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GCD.abl (cont.)
" Inputs Pins " clock PIN 12 " 1 Hz
clock (jumper) clear PIN 70 " pushbutton
S1 x3..x0 PIN 11,7,6,5 " Left Switches S6 -
1..4 x x3..x0 "
x y3..y0 PIN 4,3,2,1 " Right Switches S7 -
1..4 y y3..y0 " y "
Output Pins " LED9..LED16 PIN 35,36,37,39,40,41,43
,44 ISTYPE 'com' " LEDs
9-16 a,b,c,d,e,f,g,dp PIN 15,18,23,21,19,14,17,
24 ISTYPE 'com' " Rightmost (units)
7-segment LED display
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GCD.abl (cont.)
" INTERMEDIATE NODES PC3..PC0 NODE PC
PC3..PC0 PD3..PD0 NODE PD
PD3..PD0 PE3..PE0 NODE PE
PE3..PE0 EQUATIONS gcd1.Clk
clock gcd1.Clear clear gcd1.Z gcd2.Z
gcd1.C gcd2.C
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GCD.abl (cont.)
gcd2.clk clock gcd2.clr clear gcd2.PA3..PA0
x gcd2.PB3..PB0 y gcd2.r0ld
gcd1.r0ld gcd2.r1ld gcd1.r1ld gcd2.stld
gcd1.stld gcd2.wld gcd1.wld gcd2.msel1..msel0
gcd1.msel1..msel0 gcd2.alusel2..alusel0
gcd1.alusel2..alusel0
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GCD.abl (cont.)
d7R.D3..D0 gcd2.PE3..PE0 a,b,c,d,e,f,g
d7R.a,b,c,d,e,f,g PC
gcd2.PC3..PC0 PD gcd2.PD3..PD0 PE
gcd2.PE3..PE0 LED9..LED12
PD LED13..LED16 PC
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test_vectors(clock,clear,x,y -gt
PD,PC,PE) .C.,1,9,15 -gt 0,0,0 .C.,0,9,15
-gt 9,0,0 .C.,0,9,15 -gt 9,15,0 .C.,0,9,15
-gt 9,15,9 .C.,0,9,15 -gt 9,15,6 .C.,0,9,1
5 -gt 9,15,9 .C.,0,9,15 -gt
9,6,9 .C.,0,9,15 -gt 9,6,9 .C.,0,9,15 -gt
9,6,13 .C.,0,9,15 -gt 9,6,9 .C.,0,9,15
-gt 3,6,9 .C.,0,9,15 -gt 3,6,3 .C.,0,9,15
-gt 3,6,3 .C.,0,9,15 -gt 3,6,3 .C.,0,9,15
-gt 3,3,3 .C.,0,9,15 -gt 3,3,3 .C.,0,9,15
-gt 3,3,0 .C.,0,9,15 -gt 3,3,3 .C.,0,9,15
-gt 3,3,3 .C.,0,9,15 -gt 3,3,3 END GCD
GCD.abl (cont.)
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GCD