CS 230: Computer Organization and Assembly Language

1
CS 230 Computer Organization and Assembly
Language

• Aviral Shrivastava

Department of Computer Science and
Engineering School of Computing and
Informatics Arizona State University
Slides courtesy Prof. Yann Hang Lee, ASU, Prof.
Mary Jane Irwin, PSU, Ande Carle, UCB
2
Announcements

• Project 3
• MIPS Assembler
• Midterm Reviews
• Quiz 4
• Nov 5, 2009
• Single-cycle implementation
• Finals
• Tuesday, Dec 08, 2009

3
What is this?

• 00100111101111011111111111100000
• 10101111101111110000000000010100
• 10101111101001000000000000100000
• 10101111101001010000000000100100
• 10101111101000000000000000011000
• 10101111101000000000000000011100
• 10001111101011100000000000011100
• 10001111101110000000000000011000
• 00000001110011100000000000011001
• 00100101110010000000000000000001
• 00101001000000010000000001100101
• 10101111101010000000000000011100
• 00000000000000000111100000010010
• 00000011000011111100100000100001
• 00010100001000001111111111110111
• 10101111101110010000000000011000
• 00111100000001000001000000000000
• 10001111101001010000000000011000
• 00001100000100000000000011101100

• int main (int argc, char argv)
• int i
• int sum 0
• for (i 0 i lt 100 i i 1) sum sum i
  i
• printf ("The sum from 0 .. 100 is d\n", sum)

MIPS machine language code for a routine to
compute and print the sum of the squares of
integers between 0 and 100.
4
Abstract Implementation View

• Two types of functional units
• elements that operate on data values
  (combinational)
• elements that contain state (sequential)
• Single cycle operation
• Split memory (Harvard) model - one memory for
  instructions and one for data

Write Data
Instruction Memory
Address
Read Data
Register File
Reg Addr
Data Memory
Read Data
Address
Instruction
ALU
PC
Reg Addr
Read Data
Write Data
Reg Addr
5
Fetching Instructions

• Fetching instructions involves
• reading the instruction from the Instruction
  Memory
• updating the PC to hold the address of the next
  instruction
• PC is updated every cycle, so it does not need an
  explicit write control signal
• Instruction Memory is read every cycle, so it
  doesnt need an explicit read control signal

Add
4
Instruction Memory
Read Address
Instruction
PC
6
Executing R Format Operations

• R format operations (add, sub, slt, and, or)
• perform the indicated (by op and funct) operation
  on values in rs and rt
• store the result back into the Register File
  (into location rd)
• Note that Register File is not written every
  cycle (e.g. sw), so we need an explicit write
  control signal for the Register File

ALU control
RegWrite
Read Addr 1
Read Data 1
Register File
Read Addr 2
overflow
Instruction
zero
ALU
Write Addr
Read Data 2
Write Data
7
Load and Store Operations
8
Executing Branch Operations
Branch target address
Add
Add
4
Shift left 2
ALU control
PC
zero
(to branch control logic)
Read Addr 1
Read Data 1
Register File
Read Addr 2
Instruction
ALU
Write Addr
Read Data 2
Write Data
Sign Extend
16
32
9
Executing Jump Operations

• Jump operations have to
• replace the lower 28 bits of the PC with the
  lower 26 bits of the fetched instruction shifted
  left by 2 bits

31
25
0
J-Type
jump target address
op
Add
4
4
Jump address
Instruction Memory
Shift left 2
28
Read Address
Instruction
PC
26
10
Adding the Pieces Together
11
Adding the Branch Portion
12
Adding the Jump Portion
Jump
32
26
1
Shift left 2
28
PC431-28
0
Add
Add
4
Shift left 2
PCSrc
Instruction Memory
Read Address
Instruction
PC
13
MIPS Machine (with Controls)
Instr25-0
1
Shift left 2
32
28
26
0
PC431-28
0
Add
Add
1
4
Shift left 2
PCSrc
Jump
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
14
ALU Control

• ALU's operation based on instruction type and
  function code

ALU control input Function
000 and
001 or
010 add
110 subtract
111 set on less than
result
15
ALU Control

• Controlling the ALU makes use of multiple levels
  of decoding
• main control unit generates the ALUOp bits
• ALU control unit generates ALU control inputs

Instr op opcode funct ALUOp desired action ALU control input
lw 23 xxxxxx 00 add 010
sw 2b xxxxxx 00 add 010
beq 4 xxxxxx 01 subtract 110
add 0 100000 10 add 010
subt 0 100010 10 subtract 110
and 0 100100 10 and 000
or 0 100101 10 or 001
slt 0 101010 10 slt 111
16
ALU Control Truth Table
F5 F4 F3 F2 F1 F0 ALUOp1 ALUOp0 Op2 Op1 Op0
X X X X X X 0 0 0 1 0
X X X X X X 1 1 1 0
X X 0 0 0 0 1 0 1 0
X X 0 0 1 0 1 1 1 0
X X 0 1 0 0 1 0 0 0
X X 0 1 0 1 1 0 0 1
X X 1 0 1 0 1 1 1 1
X
X
X
X
X
X

• Can make use of more dont cares
• since ALUOp does not use the encoding 11
• since F5 and F4 are always 10
• Logic comes from the K-maps

17
ALU Control Combinational Logic

• From the truth table can design the ALU Control
  logic

18
Datapath with Control Unit
0
Add
Add
1
4
Shift left 2
PCSrc
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
19
Main Control Unit
Instr RegDst ALUSrc MemtoReg RegWr MemRd MemWr Branch ALUOp1 ALUOp2
R-type 000000
lw 100011
sw 101011
beq 000100

• Completely determined by the instruction opcode
  field
• Note that a multiplexor whose control input is 0
  has a definite action, even if it is not used in
  performing the operation

20
R-type Instruction Data/Control Flow
0
Add
Add
1
4
Shift left 2
PCSrc
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
21
Main Control Unit
Instr RegDst ALUSrc MemtoReg RegWr MemRd MemWr Branch ALUOp1 ALUOp0
R-type 000000 1 0 0 1 X 0 0 1 X
lw 100011
sw 101011
beq 000100
22
Load Word Instruction Data/Control Flow
0
Add
Add
1
4
Shift left 2
PCSrc
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
23
Main Control Unit
Instr RegDst ALUSrc MemtoReg RegWr MemRd MemWr Branch ALUOp1 ALUOp0
R-type 000000 1 0 0 1 X 0 0 1 X
lw 100011 0 1 1 1 1 0 0 0 0
sw 101011
beq 000100
24
Store Word Instruction Data/Control Flow
0
Add
Add
1
4
Shift left 2
PCSrc
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
25
Main Control Unit
Instr RegDst ALUSrc MemtoReg RegWr MemRd MemWr Branch ALUOp1 ALUOp0
R-type 000000 1 0 0 1 X 0 0 1 X
lw 100011 0 1 1 1 1 0 0 0 0
sw 101011 X 1 X 0 X 1 0 0 0
beq 000100
26
Branch Instruction Data/Control Flow
0
Add
Add
1
4
Shift left 2
PCSrc
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
27
Main Control Unit
Instr RegDst ALUSrc MemtoReg RegWr MemRd MemWr Branch ALUOp1 ALUOp0
R-type 000000 1 0 0 1 X 0 0 1 X
lw 100011 0 1 1 1 1 0 0 0 0
sw 101011 X 1 X 0 X 1 0 0 0
beq 000100 X 0 X 0 X 0 1 X 1

• Completely determined by the instruction opcode
  field
• Note that a multiplexor whose control input is 0
  has a definite action, even if it is not used in
  performing the operation

28
Control Unit Logic

• From the truth table can design the Main Control
  logic

Instr31 Instr30 Instr29 Instr28 Instr27
Instr26
R-type
lw
sw
beq
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOp0
29
Complete Datapath with Controls
Instr25-0
1
Shift left 2
32
28
26
0
PC431-28
0
Add
Add
1
4
Shift left 2
PCSrc
Jump
ALUOp
Branch
MemRead
MemtoReg
Control Unit
Instr31-26
MemWrite
ALUSrc
RegWrite
RegDst
ovf
Instr25-21
Read Addr 1
Instruction Memory
Read Data 1
Address
Register File
zero
Instr20-16
Read Addr 2
Data Memory
Read Address
Instr31-0
PC
Read Data
1
0
ALU
Write Addr
Read Data 2
0
1
Write Data
0
Instr15 -11
Write Data
1
Sign Extend
Instr15-0
ALU control
16
32
Instr5-0
30
Disadvantages of Single Cycle Implementation

• Uses the clock cycle inefficiently the clock
  cycle must be timed to accommodate the slowest
  instruction
• especially problematic for more complex
  instructions like floating point multiply
• Is wasteful of area since some functional units
  must be duplicated since they can not be shared
  during an instruction execution
• e.g., need separate adders to do PC update and
  branch target address calculations, as well as an
  ALU to do R-type arithmetic/logic operations and
  data memory address calculations

31
Yoda says

• Use your feelings, Obi-Wan, and find him you will