ERD ITWG Emerging Research Architectures - PowerPoint PPT Presentation

1 / 8
About This Presentation
Title:

ERD ITWG Emerging Research Architectures

Description:

Title: PowerPoint Presentation Subject: Color Onscreen Template Author: Zhirnov Description: VisCom Inc. 919-303-5071 919-303-5073 (fax) Last modified by – PowerPoint PPT presentation

Number of Views:74
Avg rating:3.0/5.0
Slides: 9
Provided by: zhirnov
Category:

less

Transcript and Presenter's Notes

Title: ERD ITWG Emerging Research Architectures


1
ERD ITWG Emerging Research Architectures
  • Ralph Cavin
  • Emerging Research Devices Working Group FxF
    Meeting
  • Seoul, Korea San Francisco, CA
  • Dec. 6 14, 2008

2
ITRS Emerging Research Architectures Working Group
  • Tetsuya Asai Hokkaido U.
  • George Bourianoff Intel
  • Ralph Cavin SRC
  • Erik DeBenedictis SNL
  • Michael Frank AMD
  • Dan Hammerstrom PSU
  • Rick Kiehl U. Minn.
  • Phil Kuekes HP
  • Lou Lome NASA/JPL
  • Sadas Shankar Intel
  • Rainer Waser Aachen U.
  • Franz Widdershoven NXP
  • David Yeh SRC/TI
  • Victor Zhirnov SRC
  • Ferdinand Pepper NICT

3
Significant Events in 2008
  • 2008 Intern. Conf. on IC Design and Technology
  • (Grenoble, France, June 4, 2008)
  • Invited New State Variable Device Opportunities
    for Beyond CMOS A System Perspective (R. Cavin,
    V. Zhirnov, G. Bourianoff)
  • Input from Nanoelectronic Research Initiative
  • Main Theme Architecture linkage to Logic Devices
  • Chapter to be published in ICICDT Springer Book
  • Sent to ERD group

4
Significant Events in 2008
  • IEEE/ACM Intern. Symp. on Nanoscale Architectures
    (Anaheim, CA, June 12-13, 2008)
  • Panel Perspectives on Nanoelectronics
    Materials and Architectures (S. Shankar, V.
    Zhirnov, R. Cavin)
  • Main Theme System Thermodynamics of computation

5
Significant Events in 2008
  • ITRS/SRC/NSF Forum on Emerging nano-CMOS
    Architectures in Conjunction with Frontiers in
    Extreme Computing 2020 Virtual Immersion
    Architectures (VIA-2020 ) (U. Santa Cruz, July 9
    10, 2008)
  • With participation from ITRS Design TWIG (Andrew
    Kahng)
  • Sessions
  • System Latency Minimization
  • Plenary Shannon-Moore Tradeoffs in Intelligent
    Communication (J. Rabaey)
  • Morphic Architectures
  • Plenary Graphic Processing Architectures (R.
    Koduri)
  • Computational Platforms for VIA
  • Plenary Multi-Core Communication Platform (D.
    Pham)
  • Turing-Heisenberg Rapprochement
  • Plenary Computation vis-à-vis Physics A
    Framework (R. Cavin)
  • Software Environments to support VIA
  • Plenary Creating Virtual Worlds (M. Macedonia)

6
Emerging Research Architectures Main
Categories (2007)
  • Homogeneous many-core architectures
  • Heterogeneous many-core architectures
  • Morphic architectures
  • Having a specified form or shape
  • Conveys that the computational structure is
    inspired by the physics, biology, etc. of the
    problem being addressed. Morphic systems sense,
    filter, extract features, characterize, and
    report/take action
  • Example Vision Chip, Electronic Cell etc.

These categories will be modified/updates based
on the outcome from the 2008 events
7
Emerging Research Architectures
Architecture Implementation Computational Elements Network Application Research Activity
Homogeneous Many-Core Symmetric cores CMOS Irregular/ Fixed Synthesis/GPP
Heterogeneous Asymmetric cores CMOS Irregular/ Fixed Synthesis/GPP
Heterogeneous CMOL CMOSMolecular Switches Irregular/ Fixed Synthesis/GPP
Heterogeneous Molecular Cross-bar Molecular Switches Regular/ Flexible Synthesis/GPP
Heterogeneous Check-point CMOS Ferromagnetic logic Irregular/ Fixed Synthesis/GPP
Morphic CNN CMOSSensors Regular/ Flexible Recognition/Vision
Morphic AMP FG-FET, SET Irregular/ Fixed Recognition/Vision
Morphic Bio-inspired MFDT, Spin-gain transistor Mixed Recognition Mining Synthesis
Proposal not to include in 2009 ERA, as they are
becoming mainstream in MPU and GPU design
Action Item Needs to be critically evaluated
based on results of 2008 July ERD meeting
Action Item Will be updated based on results of
the 2008 events
CMOL Molecule on CMOS architecture CNN
Cellular Nonlinear Network AMP Associative
Memory Processor
GPP General Purpose Processor FG-MOS Floating
Gate MOS devices SET single electron transistor
MFTD multiferroic tunnel diode
8
2009 ERA Proposed Changes
  • To create Memory Architecture table
  • Reason Recommendation of ERD group in 2008
  • Take out the entries for the Homogeneous
    Multi-Core and Heterogeneous Multi-core/Asymetric
    Cores
  • Reason they are becoming mainstream in MPU and
    GPU design
  • Critically evaluate the CMOL entry
  • Reason extended technical discussion at the 2008
    July ERD meeting revealed serious potential
    difficulties of CMOL
  • Morphic architectures entry will be updated
  • 2008 meetings results
  • Most recent literature search
Write a Comment
User Comments (0)
About PowerShow.com