Title: EE 587 SoC Design
1EE 587SoC Design Test
- Partha Pande
- School of EECS
- Washington State University
- pande_at_eecs.wsu.edu
2SoC Physical Design Issues Wire Inductance
3Wire Inductance
- Wide wires in clock distribution upper level
metal layers - These wires have low resistance
- Exhibit significant inductive effects
- New materials with low-resistance interconnect
4Inductance
- Complete interconnect model should include
inductance - With increasing frequency and a decrease in
resistance due to wide wires and the use of
copper, inductance will begin to influence
clocks/busses - Z R j?L
- Inductance, by definition, is for a loop not a
wire - inductance of a wire in an IC requires knowledge
of return path(s) - inductance extraction for a whole chip is
virtually impossible...
-
V
VLdi
i
dt
R
L
C
5Evolution of Interconnect Model
6Transmission Line Model
7Inductance Effects
VO
Vin
VO Zo Vin
R
L
C
Zt
Treat RC problem as a resistive divider
1 sC
wn 1/sqrt(LC) zRC/2sqrt(LC) damping factor
Zo
Zt
1 sC
(R sL)
wn2
1
s2 s2zwn wn2
s2LC sRC 1
z gt 1 we have two real poles (RC effects) z lt 1
we have two complex poles (RLC effects)
Poles are P1,2 wn - z sqrt(z2-1)
-
8Inductance Effects
9Other Inductance Effects
- For most gates Ron is in the order of K? so
typically R gtgt jwL - response is dominant by RC delay for most signals
- Only the large drivers have a small enough Ron to
allow the inductance to control the dynamic
response - clocks
- busses
- For clocks, self-inductance term can dominate the
response (especially if shielding is used) - For busses, mutual inductance term dominates and
creates noise events that could cause malfunction - For power supplies, inductance can also be a
problem due to the Ldi/dt drop (in addition to
the IR drop) as supplies scale down
10Capacitive and Inductive Noise
For most wires, j?L lt (RwireRdrive) for the
frequency and R of interest. So, for delay, L is
not a big issue currently. But ?L can be ? 20 -
30 of R so noise may be seen on adjacent line
(mutual coupling)
Dangerous scenario is a combination of localized
capacitive coupling noise and long range mutual
inductive coupling noise
-
-
Return path current
Double noise events
11Gate Driving an RLC Transmission Line
12 Propagation Delay
RtRl, LtLl, CtCl, CTCL/Ct
13Propagation Delay (Contd)
- where ? and wn are the damping factor and
natural frequency of the circuit - Function of both the interconnect and gate
impedance
14Propagation Delay (Contd)
- If the ratio of the total resistance of the line
to the lossless characteristic impedance
increases, inductive effects can be neglected - If the ratio of the driver resistance to the
lossless characteristic impedance increases,
inductive effects can be neglected - If the ratio between the time required to charge
the load capacitance through the gate and wire
resistance to the time of fight increase then
inductive effects can be neglected
15Effect of inductance on Signal Delay
16Dependence of Delay on Interconnection Length
- If the gate parasitic impedances (CL and Rtr )
are neglected then the propagation delay can be
expressed as
- For the limiting case where L ?0, the above
equation reduces to - For the limiting case R -gt0, the delay is given
by
17Repeater Insertion revisited
- Lower repeater size and less number of repeaters
- The amount of inductance effects present in an
RLC line depends on the ratio between the RC and
the LC time constants of the line - As Inductance effect increases the LC time
constant dominates the RC time constant and the
delay of the line changes from a quadratic to a
linear dependence on the line length. - Optimum number of repeaters for the minimum
propagation delay decreases
18Inductance Power Dissipation
- The dynamic power is given as
- Increasing inductance effects results in fewer
number of repeaters as well as smaller repeater
size - Significantly reduces total capacitance
- Faster rise time results in lower short-circuit
power
19Inductance Extraction
- Inductance can only be defined for a closed
current loop - The inductance of the loop is proportional to the
area of the loop - At low frequency resistive impedance dominates
- Current uses as many returns as possible to have
parallel resistances - Situation is different at higher frequencies
20Mutual Inductance
- Causes extra noise and delay effects
21Inductive Noise in a bus
- Physically, a wide bus with all the lines
switching in the same direction behaves as one
wide line - Hence, the effective inductance of a line that is
part of a bus is far larger than the
self-inductance of that line - LC time constant of the line becomes much larger
22L di/dt effects on the Power Supply
23Antenna Effects
- As each metal layer is placed on the chip during
fabrication, charge builds up on the metal layers
due to CMP1, etc. - If too much charge accumulates on gate of MOS
transistor, it could damage the oxide and short
the gate to the bulk terminal - Higher levels of metal accumulate more charge so
they are more troublesome (i.e., metal 5 is worse
than metal 1) - Need to discharge metal lines during processing
sequence to avoid transistor damage (becomes a
design/layout issue)
Metal 2
Metal 1
Areawire Areagate
Antenna Ratio
Poly
This transistor could be damaged
1. CMP is chemical mechanical polishing which is
used to planarize each layer before the next
layer is placed on the wafer.
24Preventing Antenna Effects
- A number of different approaches for antenna
repairs - Diode Insertion - Make sure all metal lines are
connected to diffusion somewhere to discharge the
metal lines during fabrication
-diodes costs area - need to optimize number
and location - causes problems for design
verification tool
n
p
Antenna diode
25Preventing Antenna Effects
- Note that there are always diodes connecting to
source/drain regions of all transistors and
charge on each layer is drained before next layer
is addedso why are we worried? - Gate input of next device may not be connected to
a diode until its too latecharge accumulation
on metal exceeds threshold
Should put antenna diode here.
Keep area of upper layer metals small near next
transistor
26Preventing Antenna Effects
- Second approach is to add buffers to interconnect
to break up long wire routes and provide more
gate area for antenna ratio - Third approach is to use metal jumpers to from
one layer of metal to another
Metal 1/polish vias (charge removed) Metal2/po
lish
27Class Presentation
- The first class presentation assignment will be
posted soon. - One of you has to present the basic concepts
discussed in the paper to the class - Presentation time 20 minutes
- After the presentation everybody has to
participate in the discussion