DAC99 Panel Proposals 506, 507, 509

1
DAC99 Panel Proposals 506, 507, 509

• Andrew B. Kahng
• January 14, 1999

2
Cell Libraries - Build vs. Buy, Static vs. Fluid

• Background
• cell libraries determine ASICdie size,
  performance, power
• factors routing access/pitch, drive strengths,
  common logic functions,
• choices silicon vendor (cost, comfort),
  3rd-party (migration, better capacity-to-cost),
  internal (control, as well as project-specific,
  on-the-fly)
• key questions (1) pros and cons of different
  libraries, library sources? (2) technical and
  business criteria for library strategy? (3)
  business and technology trends that will
  change/improve libraries in future?
• interests users, library vendors, silicon
  vendors, silicon foundries, EDA
• Structure
• (10) moderator cell libraries role in design
  flow alternatives
• (35) panelists best source of libraries for
  different customer types own library strategy
  what to consider/measure in selecting library
• (30) moderated discussion (15) audience QA

3
Cell Libraries - Build vs. Buy, Static vs. Fluid

• Panel Composition
• Organizer Emil Girzcyc, ex-Cadabra
• Moderator Kurt Keutzer, UC Berkeley
• Jeff Lewis VP Mktg, Artisan ((free) library
  vendor)
• Martin Lefebvre President, Cadabra (build your
  own library to fit product)
• Kurt Wolf Dir Mktg for EDA / library
  relationships, TSMC (foundry)
• Tony Waitz Dir Library Development, Synopsys
  (service EDA tools i/f)
• Jeff Burns IBM Austin (dynamic, on-the-fly
  libraries for max perf)
• Dave Pietromonaco Eng Mgr internal cell library
  group, HP (system house)
• Jay Maxey MTS, TI (silicon vendor provides
  process-tuned lib, correctness)

4
Design-Manufacturing Interface in DSM Era Is
Tech-Independent Design Dead?

• Background
• process capability (gates, interconnect) must be
  abstracted, consistent with design parameters and
  complexity of (e.g., SOC) design tasks
• factors reuse and increasing role of foundries
  for complex SOCs shrinking design and yield
  ramp-up times (TTM) reality of design and
  showstoppers in design for leading-edge
  technologies
• key questions (1) how to design cell/IP
  libraries? (2) design for a technology that is
  being developed? (3) what design flow minimizes
  iterations? (4) can one design robustly enough
  to be immune to technology changes? (5) how to
  take interconnect into account in SOC?
• interests IDMs, ASIC, foundries, fabless, CAD

5
Design-Manufacturing Interface in DSM Era Is
Tech-Independent Design Dead?

• Structure
• (30) moderator and panelists 5-minute
  statements of perspectives
• designer (both SOC and high-perf microprocessor)
• foundry (hand-off issues)
• 3rd-party library vendor (process-specific cell
  library design)
• analysis tool vendor (interconnect challenges)
• process modeling, yield learning (examples of
  des-mfg I/F in action)
• (60) moderated and audience Q/A

6
Design-Manufacturing Interface in DSM EraIs
Tech-Independent Design Dead?

• Panel Composition
• Organizer and Moderator Andrzej Strojwas, CMU
• Joseph Borel Exec VP RD, ST Microelectronics
  (requirements for SOC and concurrent technology /
  library design issues)
• M. Kakumu GM, Custom LSI/ASIC Div, Toshiba
  (interplay (e.g., yield ramping) between design
  and process)
• John Kibarian Pres/CEO, PDF Solutions (real-life
  yield ramp / des cycle)
• Resve Saleh Chaiman, Simplex (role of
  interconnect in design cycle)
• Mark Templeton Pres/CEO, Artisan (need to tune IP
  libs to DSM process)
• Ping Yang VP Design Services, TSMC (foundry
  viewpoint, design rule reqs for conservative and
  aggressive design scenarios)

7
Parasitic Extraction Accuracy How Much Is
Enough?

• Background
• how does the designer choose the parasitic
  extraction solution that is best for the design?
  where should effort be spent?
• example perspectives
• 3-D, silicon-exact accuracy is always essential
• accuracy requirement is determined by the overall
  design process and is less than you think
• methodology (e.g., net filtering from upstream
  analyses) efficiently provides the required
  accuracy
• key questions (1) how much accuracy is really
  necessary? (2) how to reconcile accurate
  extraction with process variations? (3) where
  is/should parasitic extraction be used and how
  important are speed, resource reqs? (4) other
  (inductance? relative vs. absolute? floating
  vs. grounded? )
• Structure
• short statements (background, perspective as to
  key issues), mostly Q/A

8
Parasitic Extraction Accuracy How Much Is
Enough?

• Panel Composition
• Organizers Mark Basel, Cadence and Paul
  Franzon, NCSU
• Moderator Paul Franzon, NCSU
• Mark Basel Architect, Cadence (what is the
  meaning of accuracy? larger picture combination
  with other analyses in a PV methodology)
• Ron Preston Circuit designer, Compaq Alpha
  (extraction requirement from circuit designers
  perspective)
• Robin Sarma TCAD support, TI DSP group (absolute
  accuracy is not the only way to achieve desired
  results
• Marty Walker VP Eng, Frequency (accurate
  extraction is essential)
• Sharad Mehrotra CAD RD, IBM Austin (captive CAD
  perspective)