Solution to HW1

1
Solution to HW1

• Name differences for local wires between NTRS97
  (below) and ITRS01 (table 62a), and explain
  reasons for such changes
• A/R ratio becomes smaller
• Copper reduces the need of a high A/R ratio in
  order to achieve a low resistance
• Reduced A/R ratio gt reduced coupling cap between
  adjacent wires
• Effective K becomes smaller
• Too optimistic in NTRS97
• Fat and tall intermediate and global wires
  specified in ITRS01 (but not NTRS97)
• Reversed scaling for interconnects

2
Homework 2

• Submit to Marilyn Saunders
• Engineering IV, 66-127CC
• Email marilyn_at_ea.ucla.edu
• Tel 5-2214
• Or email at lhe_at_ee.ucla.edu
• Due 3pm, Oct. 18th, Friday

3
Reading Assignment

• Elmore delay model (Elmore, Journal of Applied
  Physics, 1948, handout)
• Elmore delay for RC tree (Rubinsteun-Penfield-Horo
  witz,TCAD'83, handout),

4
Written Assignment

• Find the inductance matrix for the normalized RLC
  circuit model
• Assume that the inductance matrix for the full
  RLC circuit model is

A
B
C
D
E
F
3-bit bus with 2 segments per bit
La Lab Lac Lad Lae Laf
Lb Lbc Lbd Lbe Lbf
Lc Lcd Lce Lcf
Ld Lde Ldf
Le Lef
Lf
5
Written Assignment

• Assume that a long interconnect line can be
  modeled by a distributed L-type circuit model
• Prove that the number of segments does not affect
  the Elmore delay of this line
• Is the above conclusion still true if the ?type
  circuit model is used?

6
Written Assignment

• Survey of two BEM papers
• Summary for each method
• Comparison between them
• Roughly 2 pages
• References
• K. Nabors and J. White, TCAD, Nov., 1991
• FastCap A multipole accelerated 3-D capacitance
  extraction program
• W. Shi, J. Liu, N. Kakani, and T. Yu, DAC98
  (best paper award)
• A Fast Hierarchical Algorithm for 3D Capacitance
  Extraction

7
Written Assignment

• Survey of inductance sparsefication papers
• Summary for each method
• Comparison between them
• Roughly 34 pages
• References
• L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An
  Efficient Inductance Modeling for On-chip
  Interconnects,"IEEE Custom Integrated Circuits
  Conference, May 1999.
• N. Chang, S. Lin, L. He, O. S. Nakagawa, and W.
  Xie, "Clocktree RLC extraction with Efficient
  Inductance Modeling", Design Automation and Test
  in Europe, March 2000.
• Shepard, Tian, TCAD00, return-limited
  inductances a practical approach to on-chip
  inductance extraction
• Krauter, Pileggi, ICCAD95, Generating Sparse
  Partial Inductance Matrices with Guaranteed
  Stability
• Devgan, Ji and Dai, ICCAD00, how to efficiently
  capture on-chip inductance effects Introducing a
  new circuit element K
• Link provided at http//eda.ee.ucla.edu/ee298.html