Title: Comparison%20of%20Various%20Multipliers%20for%20Performance%20Issues
1Comparison of Various Multipliers for Performance
Issues
By Manto Kwan
High Speed Low Power ASIC 97.575
24 March 2003. Depart. Of Electronics
2Contents
- Introduction
- Twin-Piped Serial-Parallel Multiplier
- Array Multiplier
- Wallace Tree Multiplier
- Modified Booth Multiplier
- Combined Modified Booth-Wallace Tree Multiplier
- Conclusion
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3Introduction
- Multiplier plays an very important role in
today's digital circuits. The design of high
speed, low power consumption, less area, and low
irregularity in layout are very important. - There are various types of multipliers
- Twin-Piped Serial-Parallel Multiplier,
- Array Multiplier, Wallace Tree Multiplier,
- Modified Booth Multiplier, and
- Combined Modified Booth-Wallace Tree Multiplier.
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4Twin-Piped Serial-Parallel Multiplier
- Odd-indexed data bits and even-indexed data bits
are processed in different clock phase and
different circuits. - Results in double throughput.
- The multiplier consists of 4 units.
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5Twin-Piped Serial-Parallel Multiplier
- The multiplicand is fed in parallel. The
multiplier is fed in serial. - The product is shifted out in series.
- Use where area and power consumption is
restricted and speed is not important.
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6Array Multiplier
- Regular structure.
- Partial products are added and then shifted.
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7Wallace Tree Multiplier
- Partial Sum adders can be re-arranged in a
tree-like fashion, reducing the critical path and
the number of cells needed. - Fig. (a) Only column 3 has to add 4 bits. All
others are less complex.
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8Wallace Tree Multiplier
- Fig. (b) Half Adders (HA) in column 3 4.
- Fig.(c) Full Adders (FA) in column 3, 4, and 5
HA in column 2. - Fig. (d) Finally, HA from column 1 to 6.
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9Wallace Tree Multiplier
- Wallace Tree multiplier implementation.
- Substantial saving on larger multiplier.
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10Modified Booth Multiplier
- Reduction on number of partial product by one
half on average. - Great savings on silicon area and increase in
speed as the number of stage reduced by half.
11Modified Booth Multiplier
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12Combined Modified Booth-Wallace Tree Multiplier
- Better area performance due to Modified Booth
Algorithm and reduced delay due to Wallace Tree. - However, building a regular structure becomes a
challenge.
13Comparison of 5 different multipliers
- Wallace tree multiplier and Combined
Booth-Wallace tree multiplier have the least
delay. - Serial Parallel multiplier requires the least
area and power when speed is not important.
14Conclusion
- Each multiplier has its own advantage and
disadvantage. - Choice of a specific multiplier depends on
application and constraint on area, power, delay.
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15Design Project
- Design an 8 bit Array Multiplier
- Using Logical Effort and Logical Balance.
- Compare the power consumption and delay.
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16Tentative Schedule
- Background Research
- First half of April
- Designing
- Third week of April onward
- Simulations
- 21-30 April 2003
- Presentation
- 26-28 April 2003
- Report
- 1-5 May 2003
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17The End
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