9o e??

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9o e??µ??? ??e?t??????? ?????????ast???? sta
FPGA
VLSI II
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FPGA The chip that flip-flops
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?as???? s?ed?ast???? ?d?e?

• ???a? ef??t?? ? s?ed?asµ???
• S?ed?ast???? p??d?a??af??
• ??st??
• FPGA/CPLD ? ASIC?
• ????? ?atas?e?ast? FPGA/CPLD?
• ???a ???????e?a FPGA?
• ?????? ?atas?e???

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G?at? ?a ???s?µ?p????µe p????aµµat???µe?e?
s?s?e???

• As compared to hard-wired chips, programmable
  chips can be customized as per needs of the user
  by programming
• This convenience, coupled with the option of
  re-programming in case of problems, makes the
  programmable chips very attractive
• Other benefits include instant turnaround, low
  starting cost and low risk

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G?at? ?a ???s?µ?p????µe p????aµµat???µe?e?
s?s?e???

• As compared to programmable chips, ASIC
  (Application Specific Integrated Circuit) has a
  longer design cycle and costlier ECO (Engineering
  Change Order)
• Still, ASIC has its own market due to the added
  benefit of faster performance and lower cost if
  produced in high volume
• Programmable chips are good for medium to low
  volume products. If you need more than 10,000
  chips, go for ASIC or hard copy

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??sa???? sta FPGA

• ???s??µaste st?? t??t? ?e??? FPGA
• ?pa?te?ta? µ???? ??????? d??st?µa ??a t??
  ???p???s? e??? ?????µat??
• ???a? ? p?? d?ad?µ??? s?s?e?? sta
  epa?ap??sd????s?µa s?st?µata
• ?at?????? ??a ?p?????sµ??? se ep?ped? bit

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??µ? e??? FPGA
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??af??et???? t?p?? CLB
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??µ? t?? FPGA
???t?? S??d?se??
???ta?? t?? FPGA
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??µ??? st???e?a t?? FPGA

• Functional units
• RAM blocks (Xilinx)implement function truth
  table
• Multiplexers (Actel)build Boolean functions
  using muxes
• Logic gates, flip-flopsSuch as carry chains.
  Used for high-performance computations

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??µ??? st???e?a t?? FPGA

• Used in connecting
• The I/O of functional units to the wires
• A horizontal wire to a vertical wire
• Two wire segments to form a longer wire segment

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?a????a d??µ?????s??

• Note fixed channel widths (tracks)
• Should predict all possible connectivity
  requirements when designing the FPGA chip
• Channel -gt track -gt segment
• Segment length?
• Long carry the signal longer,less
  concatenation switches, but might waste track
• Short local connections, slow for longer
  connections

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???at?? ????te?t?????? t?? FPGA

• ??p?? ??s?da? (XC3000 XC4000)
• ?as???µe?? se ??aµµ?? (ACT3)
• T??assa ap? p??e? (SX Family)
• ?e?a?????
• ??a? d??stas?? (Garp, Chimaera)
• ??p?? p???µat??
• ?e????? d?asta????µe??

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????te?t????? ?as???? ??µ???? ????da?

• ? a???te?t????? e??a? ???s?µ? ??a
• ??? ?????p???s? t?? CLB
• ??? ap?d?s?
• ?? ????t???t?ta
• ??? ?ata????s? ?s????
• ?a ep???µ?t? ?a?a?t???st??? t?? CLB e??a?
• ?aµ??? ?ata????s? ?s????
• ????? ?a??st???s?
• ????? ?e?t???????t?ta
• ????? ep?f??e?a p???t???

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??e??e?t?µata FPGA

• ?pa?a-p????aµµat?sµ?? t?? ?d?a? s?s?e???
• ???s?µ???s? t?? ?????µat??
• ?a?a???? se s??t?µ? ??????? d??st?µa
• S?ed?asµ?? t?? ?????µat?? se s??µat??? d????aµµa
  ?a? HDL
• ?aµ??? ??st?? pa?a?????

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S?ed?ast??? ??µata
Specifications
Behavioral VHDL, C
Structural VHDL
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S?ed?ast??? ??µata
High-levelDescription
StructuralDescription
Specifications
X(ABCD) (AD)(A(BC)) Y (A(BC)AC
DA(BCD))
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S?ed?ast??? ??µata
DesignMethods
Full Custom
Standard Cell Library Design
ASIC StandardCell Design
RTL-Level Design
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S?ed?ast??? ??µata

• Algorithmic
• Encoding data, computation scheduling, balancing
  delays of components, etc.
• Gate-level
• Reduce fan-out, capacitance
• Gate duplication, buffer insertion
• Layout
• Move transistors driven by late inputs closer to
  the output

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RETIRE...
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S?ed?ast??? ???
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Detailed Design

• Choose the design entry method
• Schematic
• Gate level design
• Intuitive easy to debug
• HDL (Hardware Description Language), e.g. Verilog
  VHDL
• Descriptive portable
• Easy to modify
• Mixed HDL schematic
• Manage the design hierarchy
• Design partitioning
• Chip partitioning
• Logic partitioning
• Use vendor-supplied libraries or parameterized
  libraries to reduce design time
• Create manage user-created libraries (circuits)

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Functional Simulation

• Preparation for simulation
• Generate simulation patterns
• Waveform entry
• HDL testbench
• Generate simulation netlist
• Functional simulation
• To verify the functionality of your design only
• Simulation results
• Waveform display
• Text output
• Challenge
• Sufficient efficient test patterns

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HDL Synthesis

• Synthesis Translation Optimization
• Translate HDL design files into gate-level
  netlist
• Optimize according to your design constraints
• Area constraints
• Timing constraints
• Power constraints
• ...
• Main challenges
• Learn synthesizable coding style
• Write correct synthesizable HDL design files
• Specify reasonable design constraints
• Use HDL synthesis tool efficiently

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Design Implementation

• Implementation flow
• Netlist merging, flattening, data base building
• Design rule checking
• Logic optimization
• Block mapping placement
• Net routing
• Configuration bitstream generation
• Implementation results
• Design error or warnings
• Device utilization
• Timing reports
• Challenge
• How to reach high performance high utilization
  implementation?

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Device Programming

• Choose the appropriate configuration scheme
• SRAM-based FPGA/CPLD devices
• Downloading the bitstream via a download cable
• Programming onto a non-volatile memory device
  attaching it on the circuit board
• OTP, EPROM, EEPROM or Flash-based FPGA/CPLD
  devices
• Using hardware programmer
• ISP
• Finish the board design
• Program the device
• Challenge
• Board design
• System considerations

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HDL Design Flow

• Why HDL?
• Can express digital systems in behavior or
  structure domain, shortening the design time
• Can support all level of abstraction, including
  algorithm, RTL, gate and switch level
• Both VHDL Verilog are formal hardware
  description languages, thus portable
• Typical HDL design flow
• Use VHDL or Verilog to express digital systems
• VHDL or Verilog simulation tool is required to
  simulate your project
• Use high-level synthesis tool to obtain
  structural level design
• Then use FPGA placement routing tools to obtain
  physical FPGA netlist

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?? ?a ?????µe

• ?e????af? ?????µat?? se VHDL
• VHDL functional simulation
• ??e???? t?? s?µ?t?? e??d??
• S???es? t?? ?????µat?? se FPGA a???te?t????? t??
  Xilinx µe t? pa??t? Leonardo Spectrum (Exemplar)

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?e????af? se VHDL
library IEEE use IEEE.STD_LOGIC_1164.all entity
converter is port ( i3, i2, i1, i0 in
STD_LOGIC a, b, c, d, e, f, g out
STD_LOGIC) end converter architecture
case_description of converter is begin P1
process(i3, i2, i1, i0) variable tmp_in
STD_LOGIC_VECTOR(3 downto 0) begin tmp_in
i3 i2 i1 i0 case tmp_in is when
"0000" gt (a,b,c,d,e,f,g) lt STD_LOGIC_VECTOR'("11
11110") when "0001" gt (a,b,c,d,e,f,g) lt
STD_LOGIC_VECTOR'("1100000") when "0010" gt
(a,b,c,d,e,f,g) lt STD_LOGIC_VECTOR'("1011011")
when "0011" gt (a,b,c,d,e,f,g) lt
STD_LOGIC_VECTOR'("1110011") when "0100" gt
(a,b,c,d,e,f,g) lt STD_LOGIC_VECTOR'("1100101")
when "0101" gt (a,b,c,d,e,f,g) lt
STD_LOGIC_VECTOR'("0110111") when "0110" gt
(a,b,c,d,e,f,g) lt STD_LOGIC_VECTOR'("0111111")
when "0111" gt (a,b,c,d,e,f,g) lt
STD_LOGIC_VECTOR'("1100010") when "1000" gt
(a,b,c,d,e,f,g) lt STD_LOGIC_VECTOR'("1111111")
when "1001" gt (a,b,c,d,e,f,g) lt
STD_LOGIC_VECTOR'("1110111") when "1010" gt
(a,b,c,d,e,f,g) lt STD_LOGIC_VECTOR'("1101111")
when "1011" gt (a,b,c,d,e,f,g) lt
STD_LOGIC_VECTOR'("0111101") when "1100" gt
(a,b,c,d,e,f,g) lt STD_LOGIC_VECTOR'("0011110")
when "1101" gt (a,b,c,d,e,f,g) lt
STD_LOGIC_VECTOR'("1111001") when "1110" gt
(a,b,c,d,e,f,g) lt STD_LOGIC_VECTOR'("0011111")
when "1111" gt (a,b,c,d,e,f,g) lt
STD_LOGIC_VECTOR'("0001111") when others gt
(a,b,c,d,e,f,g) lt STD_LOGIC_vector'("0000000")
end case end process P1 end case_description
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????????e? ??????? VHDL

• ????es? d?af???? t?µ?? st?? e?s?d??? se d??f??e?
  ???????? pe???d???
• ??e???? a? ta ap?te??sµata e??a? s?st?

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??e???? ??µat?µ??f??
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?????aµµat?sµ?? t?? FPGA
module count8(clock, clear, enable, cout) input
clock, clear, enable output 70 cout reg
70 cout always _at_(posedge clear or posedge
clock) begin if (clear 1) cout 0 else
if (enable 1) cout cout 1 end endmodule...
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?????aµµat?sµ??