ECE462/562 Class Project

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ECE462/562 Class Project

• Intelligent Cache Replacement Policy
• Team member
• Chen, Kemeng Gregory A Reida

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ECE 462/562 Class Project

• Intelligent replacement policy KillLRU
• find the block that is unlikely to access (dead
  block) and replace it upon a cache miss
• Current replacement policy LRU
• passive reactive
• little use of historical information

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ECE 462/562 Class Project

• Architecture

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ECE 462/562 Class Project

• Signature generating functions
• 1. new_sig current_sig (PC of load/store)
• 2. new_sig current_sig
• (PC of load/store ltlt num_access)
• 3. new_sig last n bit of branch_history
• 4. new_sig (sum of PC of load/store) Mod n

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ECE 462/562 Class Project

• Verification
• Generate trace for L1 cache (small cache) from
  both the cold start and middle of the execution
  using Simplescalar 3.0
• Direct mapped cache 100 access
• 2-way associativity 2 sets 500 access
• 16-way associativity 32 sets 200 access
• only one set followed for 16-way

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ECE 462/562 Class Project

• Simulation
• Nine benchmarks from spec2000
• applu apsi art crafty equake gap gcc gzip swim
• Configuration
• Associativity 2 4 8
• Block size 2 4 8 (word)
• Cache size 16 K

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ECE 456/562 Class Project
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ECE 462/562 Class Project

• Analysis
• Kill policy no better performance when
  simulated without targeting on specific arrays of
  memory access compared with LRU
• Hardware signature table will be very large
• Speed kill policy may take longer time to
  execute in hardware than LRU
• Power kill policy may consume more
  power than LRU

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ECE 462/562 Class Project

• Questions?