Title: The Changing Roles of Verification and Test in the Late-Silicon Era
1The Changing Roles of Verification and Test in
the Late-Silicon Era
Tim Cheng University of California, Santa
Barbara Sanya, China December 22, 2009
2(No Transcript)
3Shifting Focus of Design Challenges
source Intel
4Harder to Produce Working Chips
- First-silicon success rate has been dropping
- Yield has been dropping for volume production and
takes longer to ramp up the yield - Better than worst-case design results in
failures w/o defects adding more burden on
testing
5Harder to Produce Working Chips
- First-silicon success rate has been dropping
- Yield has been dropping for volume production and
takes longer to ramp up the yield - Better than worst-case design results in
failures w/o defects adding more burden on
testing
Eventually,
- Every design will still have bugs after tapeout
and even after deployment, and - For every chip manufactured, some transistors are
outside spec range/non-functional, and some
encounter early-life/in-field failures
6Chip Correctness From Design Verification to
Lifetime Resiliency
System Viability and Reliability
Post-silicon validation
Hardware verification
Manufacturing test diagnosis
tapeout
production
Lifetime resiliency On-line Checking Runtime
validation
time
deployment
7Post-Si Validation Cost Trend
SourceL John Barton, Intel Invited talk at GSRC
8Dedicated Resource for Each Quality Assurance
Function Too Costly and Wasteful
DFD
DFV
DFR
DFT
DFY
9Reusing On-Chip Functional Resources for Quality
Assurance Functions
- Increasing the use of software-solution/system
resources for detecting hardware failures - Using on-chip communication and control
infrastructure for test delivery and access - Using cores to test each other
- ..
10Sharing DfX Circuitry for Multiple Quality
Assurance Functions
- Generalize DfD ckt for runtime validation
- Extend validation monitors for on-line testing
- Reuse off-line calibration circuitry for in-field
online tuning - Share off-line BIST and on-line checking
circuitry - Reuse sensors for early-life failure/wearout
detection to sense silicon data for silicon
validation and manufacturing testing
11Time-Multiplexed On-Line Checking (TMOC) for
Cost-Sensitive Applications ATS08
- Online checker implemented in embedded FPGA
- Checking one block at a time in round-robin
fashion - Not interrupting normal operation
- Case Study An H.264 Decoder design
- Checkers duplicationcomparison
- Checker fabrics eFPGA
- Significant area and power o/h reductions
12Demo TMOC on a Chip
Video and Document http//cadlab.ece.ucsb.edu/mg
ao/tmoc
13Sharing TMOC With Time-Multiplexed Assertion
Checking (TMAC)
- TMOC infrastructure can be used for HW assertion
checking as well - checking sub-blocks in round-robin fashion
without interrupting normal operation
- Using coverage metrics to guide selection of
assertions for hw implementation - Adjustable area/power overheads and
coverage/detection latency tradeoffs
14Digital-Assisted Analog Design Style Receiving
Broad Acceptance
- Digital Calibration Digitally-calibrated ADCs
RF transceivers - Goal Linearity enhancement, mismatch
compensation - Digital Adaptation Adaptive equalizer in
high-speed serial links - Goal Adapt to different operational environments
- Digitally-Intensive Design All-digital PLL
- Testing is conducted after calibration/adaptation
15Utilizing Digital Processing Unit for
Post-Silicon Validation Test
Analog path observability
Analog path controllability
- Examples
- BIST for all-digital PLL (Staszewski et. al.,
TCAS-II 07) - VCO frequency characterization (Demmerle, ITC06)
- Testable adaptive equalizer (Lin Cheng, ITC06,
Abbas et al, DATE10) - Testable RF image-reject receiver (Chang Cheng,
ATS08) - Pipelined ADC calibration/testing (Chang et al.,
ISQED09, VTS09)
15
16Example 3D Die-Stacking CMOS Image Sensor
- Architecture
- Every ADC processes signals from a XY CIS block
- An ISP processes signals from several ADCs
- Stacking
- CIS to ADC array stacking
- Face-to-Face
- ADC to ISP array stacking
- Through Silicon Via (TSV)
17Results of an ADC/TSV failure in 3D CIS
18Proposed Pixel-Interleaving Design Improves Error
Tolerance Capability
Joint work of UCSB and ITRI Ref 3D Workshop
at DATE 2010
- Alter CIS output connections outputs of nearby
sensors are connected to different ADCs - Utilize de-noise schemes to achieve error
tolerance - Suggest to interleave only the columns, not rows
- To conform to current column row decoding scheme
19Error Tolerance for 3D CIS ? Pixel-Interleaving
De-noise
- Denoise Scheme
- Average the values of two nearby, same-color,
different column pixels - Example G2 (G1G3)/2
- Error tolerant capability At most one bad pixel
within 3 nearby, same-color pixels
20Cost of Pixel-Interleaving
- Wiring network at column decoder output and at
column output - Data rearrangement at the ISP
21Pixel-Interleaving 3D CISImage Quality under
different N
M 64, N 1
M 64, N 2
M 64, N 3
PSNR 23.33dB
PSNR 23.89dB
PSNR 49.39dB
22Interleaving helps maintain image qualityand
improvement saturates after certain N
One defective ADC, results of 24 Benchmark
Images, M32
Ref Chang et al, 3D Workshop at DATE 2010
23Other New Challenges (and Research Opportunities)
- Verification, validation, and test for
error-resilient chips/systems - Coverage metrics for post-Si and system
validation Lisherness and Cheng, HLDVT 2009 - Measure of observability
- Ignored by many functional metrics
- High-level compatibility
- Efficient large-scale simulation
- Support TLM and ad-hoc functional models
- Support HLS design
24What is Flexible Electronics
- Thin-film, light-weight, and low-cost
- Bendable, durable, and large-area
- Flexible substrates
- Plastics and metal foils
- Non-photolithography manufacturing
- Ink-jet printing
- Reel-to-reel imprinting
1 Roll-to-roll process, PolyIC 2 Ink-jet
printed electronics, Phillips
25Applications of Flexible Electronics
- Applications
- Non-destructive structure detectors
- Flexible solar cells
- Flexible displays
- Biometrics Lab-on-Chip
- Wearable electronics and displays
26Key Difference with CMOS
Si MOSFET A-SiH TFT Organic TFT Oxide TFT
Process Temperature 1000 C 250 C Room Temp. 150 C
Process Technology Photo-lithography Photo-lithography Roll-to-Roll / Ink-Jet RF Sputtering
Min. Length lt 65 nm 10 µm 50 µm 10 µm
Substrate Si Wafer Glass /Plastic Plastic/ Metal Foil Glass /Plastic
Device Type N- P-type N-type P-type N-type
Mobility 1500 cm2/V-s 1 cm2/V-s 0.5 cm2/V-s gt 10 cm2/V-s
Cost/Area High Medium Low Low
Lifetime Years Months Weeks Years
27Key Reliability Challenges
- Electrical degradation (A-Si TFT)
- Prolonged bias-stress on TFTs changes their
properties and varies the threshold voltage (VTH) - Solutions low-duty ratio operation, memorizing
VTH with capacitors - Chemical degradation (Organic TFT)
- Ambient oxygen and water vapor will dope the
semiconducting material, change its properties,
and vary VTH and ION/IOFF ratio - Solutions material, packaging, substrate
28 Research Opportunities on DT for Reliable
Flexible Electronics
- Reliability simulation platform
- Reliability analysis, modeling, and simulation
- System solutions for reliability enhancement
- Robust design for unreliable devices
- Post-manufacturing self-test and self-tunable
design - Array-based test flow
- Design-for-printability for roll-to-roll process
- Substrate-aware physical design methodology
- Self-aligned layer-to-layer patterning
Huang et al, DAC 2007 Huang and Cheng,
Journal of Display Technologies, 2008 Huang
et al, DATE 2010 (joint of UCSB, U of Tokyo, and
ITRI)
29Summary
- Scaling and growing complexity challenge test and
its interaction with validation and emerging
issues of variability and reliability - Test should be part of a total quality assurance
solution - Test solutions should become more application-
and system-aware - Test should maximize sharing of DFX resources
with other post-silicon tasks - Abundant research opportunities on design and
test for reliable flexible electronics