Title: Passive Distortion Compensation for Package Level Interconnect
1Passive Distortion Compensation for Package Level
Interconnect
- Chung-Kuan Cheng
- UC San Diego
Dongsheng Ma Janet Wang Univ. of Arizona
2Outline
- Motivation
- Review of High-Speed Serial Links
- Passive Distortion Compensation
- Theory
- Implementation
- Simulation Results
- Power Management and System Integration
- Research Direction
31. Motivation ITRS Bandwidth Projection
Courtesy of Hamid Hatamkhani et al., DAC 06
- Abundant on-chip bandwidth
- Off-chip bandwidth is the bottleneck
- Many chip are I/O limited
42. Review of High-Speed Serial Links
Techniques On-Chip Off-Chip
Pre-emphasis and equalization v v
Clocked Discharging (M. Horowitz, ISVLSI03) v
Frequency Modulation (S. Wong, JSSC 03 Jose ISVLSI 05) v v
CDMA on wireline (Jongsun Kim et al.) v v
Non-linear Transmission Line (E. Hajimiri JSSC05, E.C. Kan CICC 05) v
Resistive Termination (Tsuchiya et al., EPEP M. Flynn ICCAD 05) v v
53. Passive Distortion Compensation
Distortionless Transmission Line
Typical RLC Transmission Line
- Intentionally make leakage conductance satisfy
R/GL/C - Frequency response becomes flat from DC mode to
Giga Hz
- Frequency dependent phase velocity (speed) and
attenuation
63.1 Theory Telegraphers Equations
- and correspond to attenuation
and phase velocity. Both are frequency dependent
in general.
73.1 Theory Distortionless Lines
- Distortionless transmission line
If
Both attenuation and phase velocity become
frequency independent
83.1 Theory Differential Case
Common Mode Current flowing in the same
direction
Differential Mode Current flowing in the
opposite direction
Shunt between each line to ground
Shunt between the two lines
93.2 Implementation
- Evenly add shunt resistors between the signal
line and the ground - Non-ideality
Ideal Assumption In Practice Implication
Homogeneous and distributive line Discrete shunts Whats the optimal spacing? Are the shunt resistors realizable?
Frequency independent RLGC Frequency dependent RLGC Whats the optimal frequency for the matching?
103.2 Implementation MCM trace
- MCM trace vs. On-chip interconnect
MCM
On-chip
10 cm 10 mm
Length
Series Resistance
1 O/mm 1 O/µm
Frequency dependency of line parameters
Large Small
Operation region
RLC RC
113.2 Implementation A MCM Stripline Case
- Control the signal line thickness to minimize
skin effect (cost vs. distortion) - Assume LCP dielectric
Geometry based on IBM high-end AS/400 system
123.3 Simulation Methodology
- Transient simulation in Hspice
- Each transmission line segment is modeled by
W-element using frequency-dependent tabular model - Discrete resistors
- Used CZ2D tool from IBM for RLGC extraction
- Part of IBM EIP (Electrical Interconnect
Packaging) suite. - Fast and accurate
- Ensures causality of transient simulation
133.3 Simulation RLGC vs. Frequency
R
C
L
G
Z0 78 O, delay 57.78 ps/cm
- Match at DC
- Boost up low frequency traveling speed
- Balance low frequency attenuation and high
frequency attenuation
R1MHz11.07 O/cm, L1MHz5.52e-3 µH/cm, C1MHz
0.74 pF/cm
Rshunt L1MHz/R1MHzC1MHz 669.5 O/cm
143.3 Simulation Shunt Resistor Spacing
- Number of shunt resistors N
- Resistors are implemented with embedded carbon
paste film - Spacing depends on the target data rate
153.3 Attenuation
163.3 Phase Velocity
173.3 Simulation Pulse Response
DC saturation voltage determined by the resistor
ladder
less severe ISI effect
183.3 Jitter and Eye opening for 2um case
10 cm 10 cm 20 cm 20 cm
Jitter (ps) Eye opening (volt) Jitter (ns) Eye opening (volt)
1 shunt/1 cm 1 5.565 0.42563 9.369 0.095785
Terminated with Z0 2 5.0228 0.37449 13.87 0.14595
Terminated with Rdc 3 5.8183 0.33906 12.117 0.090432
Open end 22.5 0.51 gt 70 lt 0.14
- Each shunt resistor is 669.5 ohm
- Z078 ohm
- For 10cm line, Rdc 66.9 ohm for 20 cm line,
Rdc33.5 ohm
193.3 Jitter and Eye opening for 4.5um case
10 cm 10 cm 20 cm 20 cm
Jitter (ps) Eye opening (volt) Jitter (ns) Eye opening (volt)
1 shunt/1 cm 1 22.83 0.525 23.34 0.238
Terminated with Z0 2 7.3764 0.48916 37.327 0.21423
Terminated with Rdc 3 12.026 0.57114 37.443 0.20064
Open end Unrecognizable Unrecognizable Unrecognizable Unrecognizable
- Each shunt resistor is 1232 ohm
- Z071.1 ohm
- For 10cm line, Rdc 123.2 ohm for 20 cm line,
Rdc61.6 ohm
203.3 Simulation Eye Diagrams
- W8µm/t2µm/b20µm/L10cm
- 1000 bit PRBS at 10Gbps
- W-element tabular RLGC model in HSpice
Without shunt resistors
With 10 shunts (each 669.5)
Reduced amplitude
Clear eye opening
Jitter 5.57 ps Eye opening 0.426 V
Jitter 22.5 ps Eye opening 0.51 V
213.3 Best Eye Diagram for 2um thick case
Eye opening
Jitter
Best case when each shunt is 500 ohm Jitter
4.63 ps Eye opening 0.35645 V
Jitter eye opening v.s. shunt value
223.3 Eye Diagram for 4.5um thick case when matched
at DC
Open ended
10 shunts matched at DC
Jitter 22.8 ps eye opening 0.525 V
Sleepy Eye
233.3 Best Eye Diagram for the 4.5um thick case
Eye opening
Jitter
Best case when each shunt is 500 ohm Jitter
11.97 ps Eye opening 0.44036 V
Jitter eye opening v.s. shunt value
243.3 Eye Diagram for the MCM trace
Terminated with Z0
20 shunts matched at DC
Jitter 37.237 ps Eye opening 0.214
Jitter 23.24 ps eye opening 0.238 V
254. Adaptive Power Management (APM)
- The distortionless signaling simplifies the
interface circuitry. However, the twice heavier
attenuation due to passive compensation calls for
adaptive power management - With adaptive power management, we adaptively
regulate the power supply of the transmitter
according to attenuation - The regulated supply voltage guarantees the speed
of transmission while keeping the minimal power
overhead and well-controlled bit-error rate.
264. APM Preliminary Results
274. APM Controller
284. System Integration
- The reduction of the jitter leaves larger design
margin for interface circuit design - To enable an effective and accurate
communication, the operation of transmitter and
receiver must be well synchronized. This requires
accurate clock positioning and phase locking - Synergic method will be taken to achieve mutual
compensation and joint leverage on signal
accuracy, attenuation and system power.
295. Research Direction
- Develop analysis models for the technology
- Eye diagram analysis via step responses
- Power consumption
- Optimize technologies
- Chip carrier and board technologies
- Redistribution
- Physical dimensions
- Shunts, terminators
- Prototype fabrication measurement
- More applications clock trees, buses
- Incorporate transmitter/receiver design
30The End
Thank you!