LDPC Belief Propagation Decoding with Multi-Threading and Hardware Acceleration

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LDPC Belief Propagation Decoding with
Multi-Threading and Hardware Acceleration

• Computer Architecture Project

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Low-Density Parity-Check Codes

• Member of the error correcting codes family
• LDPC codes provide performance that approaches
  the Shannon Limit
• Block and Convolutional Codes.
• Belief Propagation Algorithm for decoding

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Belief Propagation Algorithm
LLR0
LLR1
LLRn-1
Variable Nodes
Check Nodes

• Log Likelihood Ratio (LLR) A measure of how
  confident the decoder is of the received bit
  being one or zero.

• The LLR messages will propagate between the
  nodes during each decoder iteration.

• The LLR values of the Variable Nodes will
  converge towards the correct values.

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Critical Computational Path
Approximated as
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One Algorithm Implementation
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Experiment

• Locate the costly-loop and study the speedup on a
  multithreaded processor
• Experiment Hardware Accelerator Architecture

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XInC Microprocessor

• multithreaded
• 16 bit
• RISC
• 8 threads
• realtime

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Experiment Tools and Metrics

• Used supplied C-compiler to generate equivalent
  LDPC-decoder assembly code
• Instruction count as metric

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Results
Architecture Inst. Count Speedup
Single Thread 9611 Base case
ST HA 6958 1.381
Multi-Thread 1384 6.944
MT HA 1005 9.563
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