25 Pixel Array Status 19 November 2003

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25 Pixel Array Status19 November 2003
Sam Burke Sean Stromberg UCSB HEP Group
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ASIC Progress

• Tanner EDA Tools Installed
• L-Edit Pro v 10.20
• T-Spice Pro v 9.02
• Network Licensing
• Permission granted to use AMI Semiconductor 0.35
  um CMOS Process (Education Program)
• Spice Models
• Set of pdf documents on process
• Design Rules
• 590 / mm2 cost with 20 samples

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ASIC Progress

• Preliminary Specfications
• 5x5 Array of 250 um square pixels
• Signal Processing
• Charge Amplifier (97 e ENC Noise Goal)
• Analog Shaping Amplifier (Ts 500 nS)
• Descriminator (32 voltage levels)
• 18 bit Accumulator (130 Mhz shift rate, output
  )
• 3.3 Vdd _at_ 50 uA per stage
• Notes based on 4 Nov telecomference with Einer

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Preferred CMOS Structure?
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Future Plans

• Create AMI 035 D-Register and Simulate
• Inverter
• Transmission Gate Design
• For use in 18 bit ripple counter
• Do layout with L-Edit checking footprint
• Create 18bit Ripple Counter and Simulate
• Charge Amplifier Simulation

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CMOS Inverter

• Vdd 3.3 vdc
• Vswitch 50 Vdd 1.65 vdc
• Wp3Wn
• Tphl 3.4ns (high to low) tRn(Cout0.8pf)
• L5um W8um
• Tplh 3.5ns (low to high) tRp(Cout0.8pf)
• L5um W35um
• Optimize for small size ?
• Ref Baker R.J. CMOS Ch 11

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Transmission Gate

• Vdd 3.3 vdc
• Vswitch 50 Vdd ?
• Ton ?
• Toff ?
• Ref Baker R.J. CMOS Ch13

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D Flip Flop

• Simple Master / Latch Version
• 4ea Inverters 1 Trans Gate
• Master/ Slave Version?
• 4ea Inverters 4 Trans Gates
• Set and Clear Required?
• 4ea 2-Nand Gates 4 Trans Gates