Thank you!!! - PowerPoint PPT Presentation

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Thank you!!!

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Title: Research Status Author: Pao-Ann Hsiung Last modified by: Pao-Ann Hsiung Created Date: 11/21/2001 12:54:21 AM Document presentation format: – PowerPoint PPT presentation

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Title: Thank you!!!


1
Thank you!!!
  • Thanks to ACM Taipei Chapter
  • Thanks to IICM
  • Its been a great encouragement!
  • And, a force driving me to achieve more for the
    betterment of us all!

2
Current Research Work
  • Embedded Systems Group(http//rtsl.cs.ccu.edu.tw/
    embedded/)
  • Real-Time Systems Laboratory(http//rtsl.cs.ccu.e
    du.tw/)
  • National Chung Cheng University
  • Chiayi-621, Taiwan, ROC.???(Pao-Ann Hsiung)
  • January 26, 2002

3
Embedded Systems Group
  • Objectives
  • Innovative research
  • Theoretical advancements
  • Practical implementations
  • Goals
  • Design Real-Time Embedded Systems
  • Verify Real-Time Embedded Systems

4
Research Sub-Groups
  • System-on-Chip Verification (4) (with Natl
    Taiwan Univ, Dept. of Elect. Eng.)
  • Bluetooth Verification (3)(with Academia Sinica,
    Inst. of Info. Sci.)
  • Embedded Software Synthesis (3)
  • Formal Verification (1)

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8
SoC Verification
  • Informal Verification (Simulation,
    Testing)
  • Formal Verification (Model Checking)
  • How to integrate them for verifying SoC???
  • Open Verification Library (OVL)
  • assertion checks ? TCTL formulas,
  • use assume-guarantee principle

9
Bluetooth Verification
  • MSC ? Timed Automata ? SGM/RED
  • LMP (Link Manager Protocol)
  • Master/Slave Role Switch
  • ACL Connection Request
  • ACL Connection Pairing/Authentication

10
Embedded Software Synthesis
  • Larger class of applications(Free Choice Petri
    Net ? Complex Choice Petri Net)
  • Time and Memory Scheduling
  • C and Java Implementations (Tools)
  • Automatic C code generation

11
Formal Verification
  • Assume-Guarantee Reasoning
  • Automating the generation of assumptions and
    guarantees
  • Vehicle Parking Management System
  • Extension to Real-Time Systems
  • Extension to Verilog OVL Assertions

12
Thank you for your attention!
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