ECE%20697B%20(667)%20Spring%202006%20Synthesis%20and%20Verification%20of%20Digital%20Circuits

1
ECE 697B (667)Spring 2006Synthesis and
Verificationof Digital Circuits

• VLSI Design Styles

2
Implementation Choices
3
Cell-based Design (or standard cells)
Routing channel requirements are reduced by
presence of more interconnect layers
4
Standard Cell Layout Methodology 1980s
Routing channel
VDD
signals
GND
5
Synthesis Flow
a multi-stage process
6
(No Transcript)
7
Intel Pentium (IV) microprocessor
8
Array based design
9
Gate Array Sea-of-gates
Uncommited Cell
Committed Cell(4-input NOR)
10
Sea-of-gate Primitive Cells
Using oxide-isolation
Using gate-isolation
11
Sea-of-gates
Random Logic
Memory Subsystem
LSI Logic LEA300K (0.6 mm CMOS)
Courtesy LSI Logic
12
2-input mux as programmable logic block
A
0
F
B
1
S
13
Logic Cell of Actel Fuse-Based FPGA
14
Look-up Table Based Logic Cell
15
LUT-Based Logic Cell
Figure must be updated
4
C
....C
1
4
xx
xxxx
xxxx
xxxx
Bits
D
xxxx
4
control
Logic
xx
xx
D
xx
xx
function
x
x
3
xx
of
xx
D
2
xxx
D
1
Logic
xx
x
xx
function
x
x
of
x
x
xxx
F
4
Bits
xxxx
Logic
control
F
xx
xx
3
xx
function
xx
x
x
xx
F
of
xx
2
xxx
F
1
xx
xx
x
xxxxx
x
H
x
P
Multiplexer Controlled
Xilinx 4000 Series
by Configuration Program
Courtesy Xilinx
16
Array-Based Programmable Wiring
Interconnect
Point
Input/output pin
Programmed interconnection
Cell
Horizontal
tracks
Vertical tracks
17
Mesh-based Interconnect Network
Switch Box
Connect Box
InterconnectPoint
Courtesy Dehon and Wawrzyniek
18
Transistor Implementation of Mesh
Courtesy Dehon and Wawrzyniek
19
Altera MAX
From Smith97
20
Altera MAX Interconnect Architecture
row channel
column channel
LAB
Array-based (MAX 3000-7000)
Mesh-based (MAX 9000)
Courtesy Altera