Ch. 7

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Ch. 7

• Memory and Programmable Logic

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Memory and Programmable Logic

• Random-Access Memory
• Memory Decoding
• Error Detection and Correction
• Read-Only Memory
• Programmable Logic Array
• Programmable Array Logic
• Sequential Programmable Devices

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Memory

• Memory
• A device to which binary information is
  transferred for storage.
• Type of memory
• random access memory , RAM
• read-only memory, ROM
• Write operation
• Storing new information into memory
• Read operation
• Transferring the stored information out of memory

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RAM

• RAM
• The time it takes to transfer information to or
  from any desired random location is always the
  same
• Storage unitbyte
• byte8 bits
• Length of a wordmultiple of 8 bits
• wordrepresent a number, an instruction,
  alphanumeric character
• Capacity of memorytotal number of bytes

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Block diagram of memory unit

• k address linesselect one particular word
• read, writespecify the direction of transfer
• n data input lineprovide the information to be
  stored in memory
• n data output linesupplying the information
  coming out of memory

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Capacity of memory

• Range of in memory size
• 210232 words
• bytes
• K210? M220? G230 ?
• 64K216 ?2M221 ?4G232 ?
• Memory 1K x 16
• 10 bits address,16 bits in each word
• Determine the no. of bits for address

k no. of address bits m total number of words
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Control inputs to memory chip

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Memory cycle timing waveforms

• access time
• the time required to select a word and read it
• cycle time
• the time required to complete a write cycle
• access time ? cycle time
• equal to a fixed number of CPU clock
• See Fig. 7-4

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Types of memory

• The mode of access of a memory
• RAM-volatile
• Static RAM(SRAM)
• internal latch
• easier to used and shorter read and write time
• Dynamic RAM(DRAM)
• electric charges on capacitor
• less power consumption
• larger storage capacity
• ROM-nonvolatile
• Read/write time depend on the distance between
  the magnetic reader/writer and the data

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Memory Decoding

• Decoder
• select the memory word specified by the input
  address
• 2-dimensional coincident decoding is a more
  efficient decoding scheme for large memories

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Memory cell

• One bit memory cell

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4X4 RAM
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Coincident Decoding- two-dimensional selection
scheme

• Decoder with k input and 2k output requires 2k
  AND gates with k input
• k input decoder can be implemented by two k/2
  input decoders with one for column and another
  for row
• e.g., 101024 decoder can be implemented by two
  532 decoders

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Example for two-dimensional decoder
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Address multiplexing

• 64K-word memory

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Read-Only Memory

• ROMpermanent binary information is stored
• k input, n output ROM

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ROM

• No data input
• Integrated circuit ROM have one or more enable
  input
• Sometimes come with three-state outputs to
  facilitate the construction of large arrays of
  ROM

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Internal logic of 32X8 ROM
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ROM truth table

• Table 7-3 328 ROM truth table

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Programmomg the ROM according to Taable 7-3

• denote a connection in place of a dot used for
  permanent connection

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Example 7-1
Design a combinational circuit with 3-input using
a ROM. Output square(input)
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ROM implementation of Example 7-1
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Types of ROMs

• The required path in a ROM may be programmed in
  four different ways.
• mask programming (mask ROM)
• Mask is done by Fab. company during the last
  fabrication
• Customer must fill out the truth table
• High cost
• programmable read-only memory(PROM)
• allows users to program in Lab.
• the program is irreversible

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Types of ROMs

• Erasable PROM(EPROM)
• by ultraviolet light
• electrically-erasable PROM(EEPROM or E²PROM),
• by electrical signal
• can be erased without removing it from tis socket

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Types of PLD (Programmable Logic Device)
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Programmable Logic Array (PLA)

• similar to PROM
• does not provide full decoding and does not
  generate all the minterms
• decoder is replaced by an array of AND gate

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PLA with 3 inputs, 4 product terms, and two
outputs

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PLA Programming Table

• PLA Programming Table consists of three sections
• 1st, list the product terms numerically
• 2nd, specify the required path between inputs and
  AND gates
• 3rd, specifies the paths between the AND and OR
  gates

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Example 7-2

• Implement the following two Boolean functions
  with a PLA
• Simplified by K-map

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Solution of Example 7-2