A Deficit Round Robin 20MB/s Layer 2 Switch

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A Deficit Round Robin 20MB/s Layer 2 Switch

• Muraleedhara Navada
• Francois Labonte

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Fairness in Switches
Output Queued Switch

• How to provide fair bandwidth allocation at
  output link ?
• Simple FIFO favors greedy flow
• Separate flows into FIFOs at output
• Bit by Bit fair queuing
• Weighted Fair Queuing allows different weight for
  flows
• Packetized Weighted Fair Queuing (aka PGPS)
  calculates departure time for each packet

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Round-Robin bit by bit allocation
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Deficit Round Robin

• Packetized Weighted Fair Queuing is complicated
  to implement
• Deficit Round Robin keeps track of credits for
  each flow
• Flow sends according credits
• Add credits according to weight
• Essentially PWFQ at coarser level

Credits
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Credits
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Time
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Credits
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NetFPGA System
1MB SRAM

• 8 Port 10MB/s duplex ethernet
• Control FPGA (CFPGA) handles physical interface
  (MAC)
• Our design targets both the User FPGAs (UFPGA)

UFPGA1
CFPGA
10MB/s Ethernet
UFPGA0
1MB SRAM
1MB SRAM
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Design Considerations

• 4 MACs behind each port (8)
• Each flow is a unique Source Address
  Destination Address pair
• 1024 flows
• Split across FPGAs
• Each UFPGAs read incoming packets from different
  ports(0-3 and 4-7)
• tradeoff between memory storage and fairness
  across all flows

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Memory Buffer Allocation

• Static Partitioning of 1MB SRAM across 512 flows
  gives 2kbytes per flow lt 2 max size packets
• Need more dynamic allocation
• Segments smaller size means less fragmentation,
  but more pointer and list handling overhead
• 128 bytes was chosen
• Keep free segments list
• Save on-chip only pointer to head and tail of
  each flow

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P1
P2
P3
P4
P5
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P6
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MAC address Learning

• Instead of telling which MAC addresses belong to
  which port
• Learn them from the source address
• Note that our split FPGA design (reading from
  different ports) require them to communicate the
  MACs learned between them
• When destination MAC is not learned yet,
  broadcast (send to all other ports).
• So MAC learning implies broadcast capability

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Read Operation
Share SA
Master Control
Read, port
MAC Learning Flow Assignment
CFPGA Interface
Control Handler
DA, SA
Flow ID
Packet Memory Manager
DRR Engine
Flow Tail
Length, ptr
1 MB SRAM
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Write Operation
Master Control
Write, port
MAC Learning Flow Assignment
CFPGA Interface
Port REQ
Control Handler
Port GNT
Data Ready
Packet Memory Manager
DRR Engine
Head, length
Next head, length, latency
1 MB SRAM
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DRR Engine

• How to handle 512 flows and stay work conserving
• Only one flow active at any time
• DRR allocation happens on dequeuing
• Fifos contain the next flow to be serviced for
  each port
• Statistics per flow
• Weight
• Latency
• Byte sent
• Packet sent
• Packets active

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Conclusion

• A Deficit Round Robin Switch with 1k flows has
  been implemented
• Provides dynamic memory buffer allocation, MAC
  learning and broadcast
• Parallel design split across 2 chips
• Gathers statistics on flows