The Von Neumann Model

1
The Von Neumann Model

• Proposed in 1946
• Two main ideas
• components of an architecture
• how instructions are processed

2
Basic Architecture

• memory
• processor
• input
• output
• control unit

contains instructions that comprise a program
executes the instructions
orders the execution of the instructions
an instruction is a unit of work
3
Organization
4
LC-2 Organization
5
Memory

• Recall the 22 by 3 memory of Ch. 3
• more realistically, many PCs are
• 228 address space (256 MB)
• 8 bit addressability
• LC-2 is 216 by 16

6
Special Registers

• MAR memory address register
• location to be read/written
• MDR memory data register
• data value to be read/written
• what has to be asserted for a value to be written?

7
Contents of Memory/Registers
00 0 1 0 01 1 1 1 10 0 0 1 11 0 0
0 Memory
MAR MDR WE 0 0 1 1 1 1 0 0 1 0 1 1
0 1
Causes memory to be read into MDR
00 0 1 0 01 1 1 1 10 1 1 0 11 0
0 0
Causes memory to be written from MDR
8
Processing Unit

• may contain specialized functional units
• LC-2 ALU has only ADD, AND, NOT operations
• size of information processed by ALU
• is the word length of the computer
• LC-2 has 16 bit word length

9
Registers

• temporary storage used by CPU for intermediate
  values of computations
• DEC Alpha has 32 registers
• LC-2 has 8 (R0-R7)

10
Input/output

• peripherals that allow computer to be connected
  to the outside world
• get data/programs in and out
• input keyboard, mouse, scanners, disks
• output monitor, printers, disks
• floppy, hard drives, zip disks, CDs

11
Control Unit

• keeps track of current instruction in a program
  and current step in executing an instruction
• coordinates activities between components
• registers
• IR holds current instruction
• PC holds address of next instruction

12
Discuss LC-2 as an Example ofa Von Neumann
Architecture

• some registers not yet discussed
• KBSR status of keys struck
• KBDR value of key struck
• CRTSR status of monitor
• CRTDR value to be written on monitor

13
Central ideas of VN architecture

• Instructions and data are both sequences of bits
  stored in memory
• One instruction at a time is executed
  (sequentially)

14
Instruction Processing

• 2 parts
• opcode what is to be done
• operands what data is manipulated
• LC-2 instruction
• 1512 opcode
• 110 how to locate operands
• How many distinct operations in LC-2?

15
ADD Example

• opcode for ADD is 0001
• ADD requires values to be pre-stored in
  registers, then the result is stored in a
  register
• Operands from register2 and register 3, result
  put in register 1

opcode register 1 register 2 not
used register 3
1512 119 8..6
5....3 2...0
16
LDR Example

• load register with a value from memory
• causes value of 2nd register to be added to
  offset value, and value at that location is
  stored in 1st register
• opcode for LDR is 0110

opcode register 1 register2
offset
1512 119 8...6
5.0..
17
LDR contd
0110 010
011 000110
1512 119 8.6
5..0
value (2nd register offset) stored in 1st
register
contents of memory in location (R3 6) goes into
R2
called base offset addressing mode
addressing mode describes the computation needed
to yield values for operands
18
The Instruction Cycle

• Sequence of steps carried out by control unit to
  execute instructions
• called phases
• 6 phases, all may not be used by each instruction

19
Fetch-Decode-Execute Cycle

• 1. fetch gets next instruction from memory
  into IR
• MAR PC
• MDR contents of memory at location
  given in MAR
• IR MDR
• PC PC 1

20
Fetch-Decode-Execute Cycle

• 2. decode in LC-2, a 4 to 16 decoder looks at
  the 4 opcode bits and asserts the appropriate
  output line to indicate the instruction to be
  executed
• 3. evaluate address if a memory address is to
  be accessed (as in LDR) this phase computes the
  address

not needed in ADD
21
Fetch-Decode-Execute Cycle

• 4. fetch operands obtains values of operands
• 5. execute carries out instruction in ALU
• 6. store result write result to designated
• destination

LDR gets value from memory into a register
ADD gets values from registers
not needed in LDR
increment PC, go to 1
22
Changing the Execution Order

• 2 issues
• how to alter the execution order?
• how to stop at the end of a program?
• have to change the PC before the next fetch phase

23
Instruction Types

• 3 kinds of instructions
• operate (e.g., ADD)
• move data (e.g., LDR)
• control instruction (e.g., JMPR)
• control instructions load the PC during the
  execute phase

24
JMPR Example

• puts an address in the PC
• useful for executing loops or skipping around
• uses base offset addressing
• JMPR opcode is 1100

opcode not used register1
offset
1512 119 8.6
5.0
25
Tying It All TogetherExample Algorithm

• 1. Initialize a counter to 12 and a sum to 0.
• 2. If counter is 0, go to step 7.
• 3. else get next data item
• 4. add item to sum
• 5. decrement counter
• 6. Output sum is sum.
• 7. End

26
Machine Language Example
Corresponding Assembly Language

• 3000 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0
• 3001 0 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0
• 3002 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0
• 3003 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0
• 3004 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0
• 3005 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0
• 3006 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0
• 3007 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1
• 3008 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1
• 3009 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0

LEA R1, x3100 AND R3, 0 AND R2, 0 ADD R2, 12 BRz
R2, x300A LDR R4, MR1 ADD R3, R4 ADD R1, 1 ADD
R2, -1 BRnzp x3004
opcodes
27
C Example

• // assumes an array holding 12 integers
• // has been declared and initialized
• int sum 0
• for (int i 0 i lt 12 i)
• sum sum arrayi

LEA R1, x3100 AND R3, 0 AND R2, 0 ADD R2, 12 BRz
R2, x300A LDR R4, MR1 ADD R3, R4 ADD R1, 1 ADD
R2, -1 BRnzp x3004
28
Example continued
Data memory containing 12 values to sum
Register s used
3100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3101 0 0 0 0
0 0 0 0 0 0 0 0 0 0 1 0 3102 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 1 3103 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0 3104 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 3105 0 0 0
0 0 0 0 0 0 0 0 0 0 1 1 0 3106 0 0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 3107 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
0 3108 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 3109 0 0 0
0 0 0 0 0 0 0 0 0 1 0 1 0 310A 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 1 310B 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
0 310C 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
R1 address of data value R2 number of data
values left to add R3 Sum of values which have
been added R4 current value to add to the sum
29
Example continued
Contents of Registers, first time thru the loop
(in hexadecimal)
After instruction 3005
After instruction 3008
30
Example continued
Contents of Registers, 2nd time thru the loop
(in hexadecimal)
After instruction 3005
After instruction 3008
31
Example continued
Contents of Registers, 3rd time thru the loop
(in hexadecimal)
After instruction 3005
After instruction 3008
32
Example continued
Contents of Registers , 12th time thru the loop
(in hexadecimal)
After instruction 3005
After instruction 3008
33
Foundation for Programming

• When you write C programs next quarter, you
  know they are translated to assembly language by
  a compiler
• then translated to machine language to be
  executed by the hardware
• hardware consists of functional units in Von
  Neumann architecture
• functional units are made up of gates
• gates are implemented by transistors