?fa?

1
?fa?µ???? ??f?a??? ??e?t???????

• Programming Logic Devices (PLDs)
• (S?s?e??? ?????aµµat???µe??? ???????)

2
?????aµµat???µe?e? ??at??e??

• ???µ? ???? ??????s?? (ROM) ??a? sta?e???
  a???µ?? ap? p??e? AND ?a? µ?a p????aµµat???µe??
  d??ta?? p???? OR.
• ?????aµµat???µe?? ?????? ???a?a (PAL)Ò µ?a
  p????aµµat???µe?? d??ta?? ap? p??e? AND p??
  t??f?d?t??? µ?a sta?e?? d??ta?? p???? OR.
• ?????aµµat???µe??? ??????? ???a?a? (PLA) - µ?a
  p????aµµat???µe?? d??ta?? ap? p??e? AND p??
  t??f?d?t??? µ?a p????aµµat???µe?? d??ta?? p????
  OR.
• S???et? ?????aµµat???µe?? ?????? ???ta?? (CPLD)
  /?????aµµat???µe??? ???a?a? ?ed??? ????? (FPGA)
  p?? p???p???e? d?µ?? ß??pe pa???t?µa t??
  ß?ß???? ??a p????aµµat???µe?e? ??????? d?at??e??
  VLSI

3
??a PLD sa? "?a??? ???t?"
?????e? p??e?
?a?
??s?d??
???d??
p????aµµat???µe???
(?????e? ?etaß??te?)
d?a??pte?
(?????e? S??a?t?se??)
4
Ge???? d?µ? µ?a? ?a??ta??? p????aµµat???µe???
??????? (Programmable Logic Array PLA)
5
?????aµµa p???? µ?a? PLA
x
x
x
1
2
3
?????aµµat???µe?e?
S??dese??
S?st????a ?R
P
1
P
2
P
3
P
4
S?st????a ??D
x1x2x1x3'x1'x2'x3 f1
f2x1x2x1'x2'x3x1x3
6
S?????sµ??? s??µat??? d????aµµa PLA
f1x1x2x1x3'x1'x2'x3
f2x1x2x1'x2'x3x1x3
7
?a??de??µa µ?a? PAL (Programmable Array Logic)
f1x1x2x3'x1'x2x3
f2x1'x2' x1x2x3
8
S?s?e?? p????aµµat?sµ?? PLD
A PLD programming unit
9
S?s?e?as?a Plastic-leaded chip carrier (PLCC) µe
ßas?
10
??µ? ???ta??? ????p????? ?????aµµat???µe???
??????? (CPLD)
?p?s?st?µa t?p?? PAL
?p?s?st?µa t?p?? PAL
?p?s?st?µa t?p?? PAL
?p?s?st?µa t?p?? PAL
Complex Programmable ?ogic Device - CPLD
11
?µ?µa µ?a? CPLD
?p?s?st?µa t?p?? PAL
12
S?s?e?as?a ?a? p????aµµat?sµ?? CPLD


CPLD se s?s?e?as?a QFP (quad flat pack)

???? ?p?????st?
??p?µ??? ?????µa


JTAG (Joint Test Action Group) p????aµµat?sµ??
13
AlteraThe Programmable Solutions Company
Programmable Logic Devices
Intellectual Property
Development Software
14
Programmable Logic Device Families
Source Dataquest
Programmable Logic Devices (PLDs)
Gate Arrays
Cell-Based ICs
Full Custom ICs
SPLDs (PALs)
FPGAs

• Common Resources
• Configurable Logic Blocks (CLB)
• Memory Look-Up Table
• AND-OR planes
• Simple gates
• Input / Output Blocks (IOB)
• Bidirectional, latches, inverters,
  pullup/pulldowns
• Interconnect or Routing
• Local, internal feedback, and global

Acronyms SPLD Simple Prog. Logic Device PAL
Prog. Array of Logic CPLD Complex PLD FPGA
Field Prog. Gate Array
15
CPLDs and FPGAs
CPLD FPGA
Complex Programmable Logic Device
Field-Programmable Gate Array
Architecture PAL/22V10-like Gate
array-like More Combinational More Registers
RAM Density Low-to-medium Medium-to-high
0.5-10K logic gates 1K to 500K system
gates Performance Predictable timing
Application dependent Up to 200 MHz today
Up to 135MHz today Interconnect Crossbar
Incremental
16
ALTERA CPLDS

• Hierarchical PLD structure
• First level LABs (Functional blocks) LAB is
  similar to SPLDs
• Second Level Interconnections among LABs
• LAB consists of
• Product term array
• Product term distribution
• Macro-cells
• Expander product terms
• Interconnection region PIA
• EPROM/EEPROM based
• Example MAX5K, MAX7K

• Altera generic architecture

17
MAX 5000

• MAX5K Macrocell

• Three wide AND gate feed an OR gate (Sum of
  products)
• XOR gate may be used in arithmetic operations or
  in polarity selection
• One flipflop per macrocell Outputs may be
  registered
• Flipflop preset and clear are via product terms
  Clock may be either system clock or internally
  generated
• Output may be driven out or fedback
• Feedback is both local and global Local feedback
  is within macrocell and is quicker

18
MAX 5000

• MAX5000 Expander Product Term

• Number of product terms to macrocell limited
• Wider functions implemented via expander product
  terms
• Foldback NAND structure
• Inputs are from PIA, expander product term and
  macrocell feedback
• Outputs of expander product term are sent to
  other macrocell and to itself

19
??µ? µ?a? FPGA (Field Programmable Gate Array)
20
?a??de??µa ??????? blockLook-up Table (LUT)
x
1
x
x
f
1
2
1
00 01 10 11
0 1
0/1
0
0
1
0
0
1
0
0/1
f
1
1
0
0
0 1
0/1
1
1
1
0/1
(b)
f
x
x
x
x


1
2
x
1
1
2
2
x
1

0 1
1
0
f
1
x
0
1
x
2
x
Look-up Table d?? µetaß??t??
21
??a LUT t???? µetaß??t??
0 1
0 1
0 1
22
??a tµ?µa µ?a? p????aµµat?sµ???? FPGA
f1 x1x2 f2x2'x3 f f1f2
Figure 3.39 A section of a programmed FPGA
23
Custom Chips, Standard Cells, Gate Arrays
f1x1x2x1x3'x1'x2'x3
f2x1x2x1'x2'x3x1x3
??a tµ?µa µe d?? se??e? p???? se ??a standard
cell chip
24
??a pa??ta?? p???? t?p?? "sea-of-gates"
25
???p???s? ??????? s????t?s?? se s?st????a p????
t?p?? "sea-of-gates"
f1x2x3'x1x3
26
?????aµµat???µe?? PLA t?p?? NOR-NOR (????µe?a
a????sµ?t??)
f1(x1x3)(x1x2')(x1'x2x3')
f2(x1x2')(x1x3')(x1'x2)
27
PLA t?p?? NOR-NOR ??a ???p???s? se µ??f?
?????sµa ????µ????
f1x1x2x1x3'x1'x2'x3
f2x1x2x1'x2'x3'
28
PAL t?p?? NOR ???p???s? se ?????sµa ????µ????
f1x1x2x1x3'x1'x2'x3
f2x1x2x1'x2'x3'x1'x1
S?st????a NOR
29

30
H d?µ? µ?a? ROM 2mxn
Sel
0
0/1
0/1
0/1
Sel
1
0/1
0/1
0/1
Sel
a
2
0
0/1
0/1
0/1
decoder
a
1
Address
m
-to-2
a
m
m
1

Sel
2
m
1

0/1
0/1
0/1
Read
d
d
d
Data
0
n
1

n
2