Presentazione di PowerPoint

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New approach to CPC design
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It is my 1-st presentation from LNF/INFN
(Frascati)
The scientific work is still under development
and the new ideas have to be tested
Triggered by P.Campana Why results on cross-talks
obtained with small chamber in May 02 are
somehow better than with the large M0 prototype
tested in October 02?
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Id like to add
?
?

• 2 problems observed in beamtests
• have to be explained and suppressed
• rather high cross-talks from wires to pads
• - double and multiple TDC spectra

Problems mentioned here were observed already in
M2R1 and other prototypes built at CERN, as well
as in Ferraras prototypes 50 crosstalks
observed in some conditions in M3R3 in October
2002 beam-tests at operational HV
What the reason?
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Cross-talks
?
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Cross-talks along the wires (longitudal) perpend
icular to wires (transverse) Longitudal
crosstalks are less studied
and much less suppressed
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According to specification (LHCb 2000-061,
W.Riegler) Cross-capacitance Cwp will be
increased with pad size, as shown
M1 M2 M3 M4 M5
R3 Pad size (cm) Number of pads Cdet (pF) Cwp (pF) CPC 2,5 (48x4) 30.3 4.75 CPC 2.5,12.5 (24x2) 50 15 CPC 2.7,13.5 (48x2) 56 21.5 CPC 5.8x14.5 (24x2) 90 40 CPC 6.2x15.5 (24x2) 140 46
LNF M0
Cwp0.475hw (pF) where h, w are pad height and
width (cm)
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Lets measure
(very good agreement with table shown above)
Cwp measured in large M3R3 is absolutely similar
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The original idea was following Cross-talks
from wire strips to pads (longitudal) will be
reduced with grounding wire strips through
HV-capacitors
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RC-model (Rwire 90
Ohm/m)
Only capacitive coupling is taken into account
in this model Assumed that width of wire strip
is equal to cathode pad
Wire strip with 4 wires
Signal from particle
Cathode pad
current source
HV-capacitor grounded on one side, as shown
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Wire strip as a transmission line, i.e.
LC-model (first proposed by LNF group)
Cathode pad
current source
Each wire can be considered as a transmission
line Wires in strip are connected in parallel L
reduced, C increased (product LC is the same)
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Recently it has been found the wire strip is
ringing (response of wire strip in small LNF
prototype made with injector)
HV-capacitor 680pF directly grounded
f95 MHz
The ringing frequency depends on inductance in
series to HV-capacitor (what the reason?)
f60 MHz
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Cross-talk profile from wires to cathode pads in
the large M3R3 prototype
Volt. step on strip (strip is floating)
20ns/div
Pad-1 (15)
Ringing 18 ns
Central Pad
Ratio 2-nd/1-st peak 20
Pad1 (20)
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Fine waveform structure at voltage rise time
1.5ns
One can see 4 ns oscillation
High frequency is due to LC of the transmision
line itself
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Response of wire strip in small LNF prototype
made with Current Injector
Ringing 13ns
Strip is grounded through 680pF, with adding
inductance period is increased
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Equivalent circuit
1.Inductance blocks HV-capacitor effect
Wire strip
Cathode pad
Terminated end
High cross-talk
Compare to ideal case
2.Another parasite effect
Assumed
But!!!
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What LC-model shows?
with HV-capacitors grounded at inductance 3nH in
series (perhaps, can be acheaved)
2-side (peak less factor 2)
1-side strip termination with 0 Ohm
Peak0.5uA Ringing 3ns
Peak1uA Ringing 8ns
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Stray inductance (printed traces) in series to
HV-capacitors and full capacitance of the wire
strip mainly specify the ringing frequency
Green 3nH Red 300nH (can be if width of
traces 0.25mm, see M3R3)
1-side strip termination with 0 Ohm
2-side termination
Green peak1uA Red peak1uA Ringing30ns
Green peak0.5uA Red peak1uA Ringing20ns
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Correct strip termination with 377 Ohm can not
be used
1- signal at far end to capacitor
Ohm
2-side termination through 680pF At 1-side
termination amplitude will depend on signal
position along the strip (see next slides)
2- middle
3- near end
No ringing, waveforms are independed to position
of the signal source, but the highest crosstalks
will be in this case
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Inductance in series to HV-capacitors (1-side
termination with 680pF and 50 Ohm)
Same schematics No ringing Peak independ on
Lstray due to 50 Ohm
, but not enough cross-talk attenuation
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1
2
Green3nH Red100nH
Scale /-2uA 10ns/div
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Inductance in series to HV-capacitors (1-side
termination with 680pF and 0 Ohm)
Same schematics
Better attenuation, but ringing at R0
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2
3
Scale /-2uA 10ns/div
Green2nH/Ringing 200MHz Red100nH/Ringing 70MHz
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Inductance in series to HV-capacitors (2-side
termination with 680pF and 20 Ohm)
Same schematics
Good cross-talk attenuation factor at 20 Ohm High
inductance leads to ringing even at R20 Ohm and
drastically reduces cross-talk attenuation
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1
2
Red100nH/Ringing 100MHz Green3nH/No ringing
Scale /-2uA 10ns/div
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Inductance of printed trace (example)
if w0.25mm trace width (in M3R3 prototype)
h1.5mm pcb thickness l3-10cm length of
trace (in M3R3 prototype) then L100-1000nH if
w1.2cm then L5nH can be achieved
_at_ C100pF
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Ringing on wire strip can double/multiple signals
and TDC spectra
Threshold defined experimentally for wire
readout 7fC for cathode (single) 5fC
FEE noise 50e/pF is not the first reason for
threshold choice, mainly cross-talks define
threshold, at efficiency 95/gap
Dynamic range of signals in CPC is large
(100) Average signal 50fC
So, high probability for after-pulsing can be
found at bad wire strip termination and imperfect
layout in CPC at any frequency of ringing (it
depends on design)
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If CstripCwire is high?
/-2uA
Excellent result
/-0.2uA
No ringing and high cross-talk attenuation
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!
Conclusion
CPC design can be improved
following the way No ringing must be on the wire
strips at perfect design 1.No wire segmentation
is needed in CPC design - one of the effective
way No HV-capacitors and resistorrs (cheaper and
much easy design), wires are connected to one
HV-resistor. Minimisation of the trace
inductances has to be done in the Combined
readout chambers, which dumps effect of low
impedance. 2.Double Cathode Readout scheme,
perhaps, can be used in some cases below M3R3
also effective way at large Cwires (it allows
increase threshold at fixed HV) already tested in
M1R1 with excelent results (because very low Cwp
and good attenuation of the cross-talks from
wires)
Happy end ?
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Summary
Voltage zero must be on the wire strips at
perfect CPC design, i.e.
M1 M2 M3 M4 M5
R3 Pad size (cm) Number of pads Cdet (pF) Cwp (pF) CPC 2,5 (48x4) 30.3 4.75 CPC 2.5,12.5 (24x2) 50 15 CPC 2.7,13.5 (48x2) 56 21.5 CPC 5.8x14.5 (24x2) 90 40 CPC 6.2x15.5 (24x2) 140 46
LNF M0
?
Single CRO. No wire segmentation
Double Cathode readout (CRO) below M3R3. No wire
segmentation