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Title: Fast and Scalable Priority Queue Architecture for High Speed Network Switches Author: ranjita Last modified by: Created Date: 7/13/1999 6:08:26 PM – PowerPoint PPT presentation

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Title: Outline


1
Outline
  • Systolic Array
  • Binary Heap
  • Pipelined Heap
  • Hardware Design

2
The Systolic Array Priority Queue
Highest value
New value
Block 1
Block 2
Block 3
Block n
Permanent Data Register
Temporary Register
NON-INCREASING PRIORITY VALUES
n 1000 Hardware required 1000 comparators,
2000 registers. Performance constant time.
3
The Binary Heap Priority Queue
1
16
2
3
14
10
4
5
6
7
7
3
4
8
8
9
10
11
12
2
3
5
7
3
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
16
14
10
7
7
3
3
2
4
3
5
8
VALUE
n 1000 Hardware required 1 comparator, 1
register, 1 SRAM. Performance O(log n).
4
The Pipelined-Heap
  • Modified binary heap data structure
  • Constant-time operation. Similar to the Systolic
    Array.
  • Good hardware scalability. Similar to the Binary
    Heap.

5
P-heap Data Structure (B,T)
6
The Enqueue (Insert) Operation
operation
1
position
value
1
operation
position
value
16
enq
9
1
16
2
3
2
3
14
10
14
10
enq
9
2
4
5
6
7
4
5
6
7
8
7
3
8
7
3
8
9
10
11
12
13
14
15
8
9
10
11
12
13
14
15
2
4
5
2
4
5
(a) local-enqueue(1)
(b) local-enqueue(2)
7
Enqueue (contd)
1
operation
position
value
operation
1
position
value
16
16
2
3
2
3
14
10
14
10
4
5
6
7
4
5
6
7
8
9
3
8
7
3
enq
9
5
8
9
10
11
12
13
14
15
8
9
10
11
12
13
14
15
2
4
5
enq
7
10
2
4
5
(d) local-enqueue(4)
(c) local-enqueue(3)
operation
1
position
value
16
2
3
14
10
4
5
6
7
8
9
3
8
9
10
11
12
13
14
15
2
4
5
7
(e)
8
The Dequeue (Delete) Operation
1
operation
position
value
deq
1
2
3
14
10
4
5
6
7
8
7
3
8
9
10
11
12
13
14
15
2
4
5
(b) local-dequeue(1)
9
Dequeue (contd)
operation
position
value
1
1
operation
position
value
14
14
2
3
2
3
8
10
10
deq
2
4
5
6
7
4
5
6
7
7
3
deq
4
8
7
3
8
9
10
11
12
13
14
15
8
9
10
11
12
13
14
15
2
4
5
2
4
5
(d) local-dequeue(3)
(c) local-dequeue(2)
operation
position
value
1
14
2
3
8
10
4
5
6
7
4
7
3
8
9
10
11
12
13
14
15
2
5
(e)
10
Pipelined Operation
level
level
1
1
2
2
3
3
4
4
5
5
6
6
level
level
1
1
2
2
3
3
4
4
5
5
6
6
11
Hardware Requirements
  • log N SRAMs represent the Binary Array B, N
    size of the P-heap .
  • log N registers represent the Token Array T.
  • log N comparators required, one for each level of
    the P-heap.
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