Digital System Design 1

1
Digital System Design 1

• Hardware Realizations

2
Introduction

• The next step in the design process is to
  translate AHPL control sequence into hardware.
• Another major part of the design process is the
  development of the control unit.
• This section deals with the hardwired approach to
  control unit.
• Another approach is to use micro-programmed
  control unit.

3
Starting, Stopping, and Resetting

• One of the more subtle problems associated with
  the design of control unit is how to get it
  started.
• Assumed control unit design (1 flip-flop per
  control step) once a single-clock-period level
  has been established at the input to any single
  flip-flop, the desired sequence of levels will
  propagate through the sequence of control
  flip-flops.
• To start operations at step 1, flip-flop 1 of the
  control unit must be set and all others must be
  reset.
• This is accomplished by using SET and RESET
  inputs of the flip-flops of control unit
• Reset line will be connected to the
• SET input of flip-flop 1, and to the
• RESET input of all other flip-flops in control
  unit.

4
Starting, Stopping, and Resetting

• The line reset will be held active as long as the
  reset button is pushed.
• When the button is released the next clock pulse
  will advance control from step 1 to step 2, and
  the sequence will proceed from there.
• With this method the system will automatically
  start through its sequence after being reset.

5
Starting, Stopping, and Resetting

• If it is desirable for the system to remain in a
  reset state while preparations for the new
  operating cycle are carried then this requires
  that step 1 be a wait state. This system will
  remain in the wait state until the start signal
  as shown in Figure 7.1.

• Implementation of RIC step 1.
• (start)/(1).
• Start of main sequence

6
Starting, Stopping, and Resetting

• Figure 7.2 shows the realization of the first few
  steps of a typical control sequence with both
  start and reset lines.
• In addition it shows the timing of typical
  reset-start sequence in which it was assumed that
  the system happened to be at the step 3 of the
  sequence at the time of the reset.

7
Reset-start sequence
8
Starting, Stopping, and Resetting

• When start goes high, control moves to step 2 to
  start the normal sequence. This reset action is
  indicated by the statement
• CONTROLRESET(1)after the END SEQEUNCE statement
  number in parenthesis indicates control step to
  which the system returns when reset.

9
Starting, Stopping, and Resetting

• Resetting the system when first turned on.
• Care must be taken to ensure that the system when
  first turned on does not start with the devices
  at random states.
• Reset line is driven active as soon as the power
  is first applied and held there for short period
  of time but long enough for the power supplies
  to reach steady state and the clock oscillator to
  stabilize.
• The reset line then goes inactive automatically
  and the system proceeds with its normal sequence
  or waits for start signal.

10
Starting, Stopping, and Resetting

• Starting/Resetting the system when in the HALT
  state.
• The easiest implementation HLT instruction is
  through DEAD END indicating that propagation of
  the control level is simply terminated.
• Hardware implementation of control steps 70 and
  71 which branch conditionally to the DEAD END at
  step 78 is shown in Figure 7.3.
• The syntax of DEAD END represents no hardware but
  indicates that nothing is connected to the output
  of corresponding control step.
• Because DEAD END as described will leave all
  control flip-flops reset, the computer cannot be
  started again without a control reset to enable
  step 1.

11
Hardware Implementation of DEAD END
12
Starting, Stopping, and Resetting

• If a reset operation affected nothing but the
  control unit previously described behavior would
  have been satisfactory.
• However, computer reset is used to shut
  everything down and start over when something
  goes wrong.
• In addition to control unit other sub-systems may
  be reset such as I/O devices, interrupt system,
  status indicators, and even the data registers.
• HLT is often used to stop a program to give the
  operator a chance to intervene without otherwise
  affecting the status of program.
• Computer reset is thus undesirable.
• HALT therefore will be implemented by
• returning the control to step 1, and
• Wait for start signal
• Without otherwise affect the status of the
  computer. This is done at step 71 as shown in
  Fig. 7.4. and step 72 is eliminated.

13
Starting, Stopping, and Resetting

• Implementation of HLT by return to Step 1

14
Starting, Stopping, and Resetting

• Timing of the start signal.
• Modern computers can execute an instruction in a
  few microseconds or even nanoseconds and can
  execute a complete program in a small fraction of
  few a second.
• If a start signal is derived directly from a
  manual push button, the computer might complete
  the program, execute a HALT, and return to step 1
  before the button has been released, in which
  event it would start again. Such false restarts
  can be prevented by the use of a single-level
  generator.

15
Starting, Stopping, and Resetting

• single-level generator
• It can be described by three statements included
  following END SEQUNCE. It requires
• two memory elements stff and slf, and a
• CTERM slstart to provide a control connection to
  the implementation of the control sequence
• END SEQUENCE
• CONTROLRESET(1)
• stff ? start
• slf ? stff
• slstart stff ? slf.
• END.

16
Starting, Stopping, and Resetting

• stff flip-flop accomplishes synchronization of
  start with the clock.
• Implementation of the partial hardware
  description just given is shown in Fig. 7.5 with
  the corresponding timing diagram.
• Note that slstart is 1 for only once
  clock-period. It remains 0 until stff goes to 1
  and returns 0 as soon as slf goes to 1.

17
Starting, Stopping, and Resetting

• Single-start-level generation

18
Starting, Stopping, and Resetting

• The hardware technique just described will be
  adequate for most digital systems including
  computers.
• However, there are software aspects to be
  considered in starting and resetting a computer.
• A control unit can basically do just one think
• Read an instruction and execute it.
• Computer cannot be started in any useful sense
  unless it has a program to start executing.
• To provide this software component of the
  start/reset process, most CPUs include a ROM
  containing a start-up program that will at the
  very minimum allow the user to enter commands
  through keyboard.

19
Starting, Stopping, and Resetting

• On power up or reset
• The reset line in addition to
• Resetting the control unit to the start of the
  fetch sequence
• Will reset the program counter to the address of
  the first instruction of the start-up program.
• Start-up program will
• Establish appropriate starting conditions in the
  system, and
• Turn control over to the operating system
  software.
• Note that start-up program is
• Part of the CPU itself, transparent to the user,
  and
• It is located in a separate address space
  accessible only during start-up and reset.
• Because computer has its initialization steps
  built in, there is rarely any need for a separate
  start button. A single reset button is sufficient
  to start the computer over and bring it to a
  condition where it is ready to start accepting
  commands form the user.

20
Multiperiod Operations

• Assumption in development of control sequence for
  RIC was that all transfer operations could be
  completed in one clock cycle.
• There are cases in which trasfers or logic
  operations may require more than one clock
  period
• Memory access.
• Typically RAM is made in technology that is
  slower than register memory due to cost.
• Majority of transfers involve registers and the
  clock rate is set to accommodate this fact.
• Slower transfers will thus requires multiple
  clock cycles.

21
Multiperiod Operations

• Many different technologies can be used or RAM.
  These technologies differ greatly in signal and
  timing requirements.
• In terms of control sequence steps required to
  control them majority of memory systems can be
  grouped into three categories
• Clocked,
• Slow synchronous, and
• Asynchronous.

22
Multiperiod Operations

• Clocked memory
• Clocked memory is logically equivalent to an
  array of clocked registers.
• Such memory is fully compatible in speed with the
  control unit.
• General model of clocked memory is depicted in
  Fig. 3.13

DATA IN
Address Register
DCD(AR)
write
M
Decoder
n bits AR
....
n lines
2n lines
DATA OUT
23
Clocked Memory

• Clocked Memory has
• Address lines
• Input lines
• Output lines
• Write enable a single control line which is
  equivalent to the clock line for a register.
• Clocked Memories are usually small arrays of
  registers that will be located on the same VLSI
  chip as the CPU (e.g., cache).
• AHPL notation that characterizes memory transfers
  of Clocked memory is given bellow
• MD ? BUSFN(MDCD(MA)) // memory read
• MDCD(MA) ? MD // memory write

24
Synchronous and Asynchronous Memory

• Memory access for this type of memory is more
  than one clocke period.
• Typical technology for synchronous memory is MOS
  memory.
• An AHPL description of the internal functioning
  of memory package is not required for modeling
  the device as slow as synchronous memory.
• However, it is important to interpret the
  input-output specifications of the package in
  terms of the timing and AHPL description of the
  CPU.

25
Synchronous and Asynchronous Memory

• Let assume a hypothetical case where CPU has a
  clock frequency approximately three times the
  sped of the available memory.
• Figure 7.6 depicts typical slow synchronous
  memory model organized as 64K 32-bit words.

26
Synchronous and Asynchronous Memory

• Addresses are provided on a 16-bit ADBUS and data
  are transferred along a 32 bit bi-directional bus
  DBUS. The line, read will be 1 for a memory read
  operation and 0 for memory write. The ADBUS and
  read lines will typically be required to be
  stable for a period of time before enable goes to
  1 initiating the memory operation.

DBUS
SM 64K X 32
DECODER
32
ASSBUS16
read
control
enable
27
Memory Module Example

• A memory module similar to the one depicted in
  the previous figure has a nominal speed of 200
  MHz. This memory is used with an implementation
  of RIC with a clock rate that will be assumed to
  be 500 MHz.
• A closer look at the memory specifications
  indicates that the address and read lines must be
  stable 0.01 µsec ahead before enable goes to 1.
• In the worst case the output data in read
  operation will not be available until 0.035 µsec
  after the onset of enable.
• Write typical control sequences that will
  accomplish properly timed read and write
  operations within this version of RIC.

28
Memory Module Example

• Solution
• The timing requirements are shown in Fig. 7.7
  superimposed in three RIC clock periods.

29
Memory Module Example

• If
• MA is loaded by the left most clock pulse, and
• read 1 during the first clock cycle,
• Then
• ADBUS and read signals will stabilize at least
  0.01 µsec prior to an enable signal that might be
  turned on during the second clock period.
• If enable does go to 1 during the second clock
  period the data will be available to be triggered
  into a RIC register by the clock pulse at the end
  of the third period.
• Even though we have no AHPL description of the
  memory module, we can describe in AHPL the RIC
  steps necessary to interface with these memory
  specifications.

30
Memory Module Example

• Because of the bus and separate control lines the
  memory must be declared as a separate module and
  the communication lines must be added to the
  declarations for RIC
• OUTPUTS ADBUS16 read enable.
• COMBUSES DBUS32.
• These lines could be similarly be declared as
  INPUTS and COMBUSES in the description of the
  memory module.

31
Memory Module Example

• It is assumed that ADBUS will be driven by the
  low-order 16 bits of MA, as specified by the
  statement
• END SEQEUENCE
• ADBUS MA823
• Typical read sequence would be
• MA ? PC.
• read 1.
• enable 1 read 1
• enable 1 read 1 MD ? DBUS.

32
Memory Module Example

• MA ? PC.
• read 1.
• enable 1 read 1
• enable 1 read 1 MD ? DBUS.

• The clock pulse at the end of the step 2
  establishes the address in MA and thus on ADBUS.
• After a delay of 1 clock period from read signal
  at step 4 enable is set to 1 and read continues
  to be one.
• This condition is held through the step 5 when
  the data is transferred form the DBUS to MD
  register.
• Note that data becomes available after 2 clock
  cycles form the time enable was set to 1 to
  accommodate memory specifications.

33
Memory Module Example

• A typical write sequence would appear as follows
• MD ? AC.
• read 0.
• enable 1 read 0
• DBUS MD enable 1 read 0.

34
Asynchronous Memory

• Asynchronous Memory Model implies the existence
  of a control line on which the memory will inform
  the CPU that data are available.
• Control line not synchronized to the CPU clock.
• Some synchronization mechanisms is necessary.

35
Asynchronous Memory

• Advantage of slow synchronous memory is that it
  does not require any additional control input.
• It is based on the worst case response of the
  memory to a request for data and times the data
  transfer accordingly.
• An example of asynchronous memory module that can
  be interfaced to a CPU with 16-bit word length is
  shown in the next slide.

36
Asynchronous Memory

• Organization of asynchronous memory module.

MODULE (MEMORY)
M 8K X 16
MAR13
MDR16
MEMADBUS13
DBUS16
read
ack
control
write
37
Asynchronous Memory

• Active level for input control lines (read and
  write) and output control line (ack) is logical
  1.
• CPU sees the memory only in terms of
  communications lines.
• Declaration Section
• INPUTS ack.
• OUTPUTS read, write.
• COMBUSES MEMADBUS13 DBUS16.

38
Asynchronous Memory

• MA register is not necessarily needed in the CPU.
• Alternatively output of registers involved can be
  transferred directly to MEMADBUS.
• Desirable to retain MD register since this
  register can be often be used to store an
  argument after a memory cycle is complete, or
  store an argument not obtained from memory.
• Typical sequence for fetching an instruction from
  the asynchronous memory
• MEMADBUS PC read 1(ack)/(2).
• IR ? DBUS.
• Continue

39
Instruction fetch control with asynchronous memory

40
Instruction fetch control with asynchronous memory

• Control holds at step 2 until ack becomes active
  (goes to 1).
• It is necessary that next memory reference does
  not being until ack has return to 0.
• Adding a step to check for this would result in
  what is called a completely responsive handshake.
• In many cases multi-period delays can be
  encountered in combinational logic units within
  the CPU itself. Typical example is ADDER.

41
Example of Slow Adder

• Consider a 32-bit computer with a clock rate of 5
  MHz (0.2 µsec period) but with an adder with a
  worst case propagation delay of 0.5 µsec. Write
  partial control sequence for execution of
  addition that will allow for the adder delay but
  will not slow down other memory reference
  operations, in particular AND and MVT.

42
Example of Slow Adder

• Solution
• It is necessary to separate the step executing
  addition from the execution of the other
  instructions. This is accomplished by the
  following partial control sequence, which
  explicitly shows AND, MVT and ADD.
• ? (DCD(IR03))/(18,19,29,other operations).
• ABUS MD OBUS ABUS AC ? OBUS ? (24).
• BBUS AC ABUS MD OBUS ABUS ? BBUSAC ?
  OBUS ? (24).
• BBUS AC ABUS MDOBUS ADD132(ABUSBBUSc
  in) AC ? OBUScff ? ADD0(ABUSBBUScin) ?
  (24).

43
Example of Slow Adder

• To complete the solution step 20 in the previous
  AHPL sequence must be replaced by a sequence of
  three steps that will implement 0.6 sec delay
  before the result of addition is clocked into the
  accumulator and carry flip-flop. The AND and MVT
  operations are still accomplished in one clock
  period.
• Note that the flags other than cff are omitted
  for clarity.
• 20-1 BBUS AC ABUS MD.
• 20-2 BBUS AC ABUS MD.
• 20-3 BBUS AC ABUS MD OBUS
  ADD132(ABUSBBUScin) AC ? OBUS cff ?
  ADD0(ABUSBBUScin) ? (24).

44
Example of Slow Adder

• Where propagation through combinational logic
  requires more than two or three clock periods, it
  may be useful to declare a counter to count the
  waiting clock periods.
• In the next example 32 clock periods are allowed
  for completion of a slow operation.
• CNT ? 5 ? 0.
• ABUS MD BBUS ACOBUS SLOWOP(ABUSBBUS)AC
  (?/CNT) ? OBUS CNT ? INC(CNT)(?/CNT)/(21).
• continue

45
Propagation Delays and Clock Rate

• Delays are provided by control flip-flop to allow
  the results of previous transfers to propagate.
• Closer look at what kind of delays may be
  encountered and what other factors may be
  involved.
• To illustrate the issues lets consider a
  following 2 steps that might be encountered in
  the multiplication sequence of an 16-bit computer
  employing a bus organization similar to that of
  RIC.

46
Propagation Delays and Clock Rate

1. BBUS MD OBUS BBUS AC ? OBUS.
2. ABUS AC OBUS (ABUS!ABUS)(AC0, AC0)
   MQ ? OBUS.

• The two steps begin the conversion of a twos
  complement argument to a sign-magnitude form.
• At step 6 argument is transferred to AC.
• At step 7, if the number is positive (AC0 0),
  AC is transferred into multiplier-quotient
  register MQ, otherwise a bit-by-bit complement of
  AC is transferred.
• Next Figure shows the control and data circuitry
  involved in these transfers, and a partial timing
  diagram.

47
Propagation Delays and Clock Rate

• Each gate/element of the circuit realization
  introduces delays.
• There will always be a difference in delays
  between specific logic elements. However, within
  certain family/technology (e.g., TTL) these
  delays are approximately uniform. On the other
  hand some other technologies (e.g., MOS) this
  variability creates more complications.
• A thorough treatment of this issue requires
  circuit analysis and, therefore it is outside the
  scope of this course.
• Nevertheless, to understand the relation between
  path delay and clock rate, we assume the
  hypothetical situation in which there exists a
  uniform delay, ?, for all logic elements.

48
Propagation Delays in a Transfer
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