CPLD Competition - PowerPoint PPT Presentation

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CPLD Competition

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CPLD Competition – PowerPoint PPT presentation

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Title: CPLD Competition


1
CPLD Competition
2
Session Objectives
  • Review Strengths Weaknesses of key competitors
  • Lattice
  • Vantis
  • Altera
  • Highlights areas to attack and win

3
Competitor Profile Vantis (AMD)
  • Old AMD PLD division
  • now a separate fabless company
  • dependent on AMD fabs ( UMC for FPGA in 98)
  • SPLDs and CPLDs now announced new VF1 FPGA
    line
  • Minimal software, customer service functions
  • management focused only on components, not
    solutions
  • relies on AMD for process development
  • Dropped down to 4rd largest PLD company
  • fell from 3rd in 97 behind Lattice
  • dependent on declining SPLD sales

4
Vantis Thrust Products
  • Mach 4LV 3.3V Low Mid density ISP
  • 32 to 256 macrocells
  • speeds to 7.5ns (slower than 5V devices)
  • good JTAG support
  • Mach 5LV 3.3V High-density ISP
  • 128 to 512 macrocells
  • raw speeds to 7.5ns, but only specific
    input-output paths
  • good JTAG support
  • Other products
  • 5V versions of Mach4, Mach5
  • Mach 1,2,3 Low density, some with ISP retrofit

5
Vantis Weaknesses (Present)
  • Clumsy Software
  • clumsy software developed by 3rd party (MINC)
  • re-starting in-house SW group (little effect in
    short term)
  • poor support for Mach5/LV
  • High prices due to high cost structure
  • 0.35um process has 0.5um feature size
  • Mach5/LV difficult to achieve speed/utilization
  • path-dependent delays
  • block-localized features cause routing
    difficulties
  • power reduction, output enables

6
Vantis Weaknesses (Future)
  • Concern over future plans
  • will business be sold (and obsoleted)?
  • reference Intel PLDs sold to Altera and
    obsoleted
  • Reduced CPLD focus
  • resources consumed by FPGA launch
  • slow cost migration, product improvements,
    software improvements

7
Vantis Attack Points
  • Attack the software
  • what is the software roadmap ?
  • Attack device volume availability
  • enough priority/capacity from AMD fabs?
  • Attack Mach5/LV architectural limitations
  • block-localized power reduction, OEs restricts
    fitting and routability
  • complex 3-tier routing structure, path-dependent
    timing
  • Attack technical support
  • call Vantis, Minc, or ? for routing issues

8
Competitor Profile Lattice
  • 1st with ISP CPLD, but an incomplete solution
  • pin-locking issues
  • old fashioned architecture
  • Non-standard ISP interface (proprietary non-JTAG)
  • Biggest supplier of ISP CPLDs
  • several different but similar CPLD families
  • 1997 CPLD market share is about 20
  • Reputation for inadequate software solution

9
Lattice Thrust Products
  • ispLSI2000V
  • 3.3v ISP (de-rated 5V parts)
  • 2032V offers no power savings over same speed 5V
    2032
  • latch-up risk in mixed 3.3V/5V systems
  • higher cost, slower speed grades than 5V versions
  • ispLSI1000E/2000
  • 32 to 192 macrocells
  • improved routing, but not enough
  • Other products
  • ispLSI3000 large difficult-to-use (192 to 320
    macrocells)
  • ispLSI6000 192 macrocells 4.6 Kbit RAM

10
Lattice Weaknesses (Present)
  • Software performance
  • hampered by the restrictive silicon architecture
  • ease of use issues
  • pin-locking issues
  • poor routing at high utilization
  • Restrictive, 6-year old architecture
  • limited product-term allocation options
  • no individual output enables (OE)
  • block-localized clock signals

11
Lattice Weaknesses (Future)
  • Proprietary, non-standard ISP interface
    (ispLSI1K/2K)
  • difficult board integration with JTAG components
  • Limited to CPLD devices only
  • against industry trend toward a single logic
    vendor

12
Lattice Attack Points
  • Attack 3.3V IC deficiencies
  • latch-up risk (requires significant design effort
    to compensate)
  • no or minimal power savings over 5V
  • slower, higher price
  • Attack software capability
  • why cant use more than 80 device utilization?
  • Attack EEPROM process roadmap
  • what is the long-term process migration path?
  • Lack of JTAG on lead products (ispLSI 1K/2K)

13
Competitor Profile Altera
  • Largest supplier of CPLDs
  • note Flex 8K and 10K are not CPLDs
  • Company focused on IC/software technology
  • not focused on solutions or customer support

14
Altera Thrust Products
  • Max7000A
  • 3.3V ISP
  • no enhancements over 7000S, only fixes
  • Max7000S
  • old Max7000(E), but with ISP
  • 32 to 256 macrocells
  • Flex10K
  • really an FPGA, not CPLD
  • Other products
  • Max9000 300 to 560 macrocells, with ISP
  • Flex 8K FPGAs called CPLDs

15
Altera Weaknesses (Present)
  • Pin-locking is well-known issue
  • especially gt 100 macrocells
  • EEPROM-based sparse routing matrix
  • 2nd time fitting is not pin-locking
  • Altera measures software ability to refit the
    same design to locked pins
  • veteran Max7K users burnt by pin-locking problem
  • 7-year-old basic architecture
  • less flexible vs. XC9500 in product-term
    allocation
  • no individual (p-term) output enables
  • only 2 global clocks

16
Altera Weaknesses (Future)
  • Proprietary EEPROM technology pushed to its
    limits?
  • persistent problems with new TSMC fab after 3
    years
  • slow and problem-prone roll-out of Max7000S
  • Market trend is for standard design language
  • move to VHDL erodes AHDL design wins
  • Architecture problems hidden by software
  • auto-picks bigger devices to reduce utilization
  • error messages say No very nicely

17
Altera Attack Points
  • Attack AHDL fortress
  • no design portability
  • convert AHDL designs to VHDL
  • sell Foundation with VHDL upgrade
  • Attack reliance on old architectures and
    processes
  • XC9500 is new technology, new benefits
  • Attack ISP device availability, quality
  • sampled defective devices to customers with
    charge loss problems
  • 3 year delay on Max7000S family rollout
  • only 100 program/erase cycles, 10 year data
    retention

18
Reference Materials
19
Pin-Locking Comparisons
Xilinx XC9500
Altera Max7KS
Lattice 1K/2K/3K
AMD Mach5
Routability Function block fan-in Bi-directional
individual product term allocation Maximum
pterms/MCell
Excellent 36 Yes 90
Good 36 No 32
Poor 18/24 No 20
Good 32 No 32
Notes Increasingly worse with density
20
JTAG Comparison
JTAG Instruction
Altera Max7KS
Xilinx XC9500
Lattice isp
AMD Mach5
Capability
Extest Sample/Preload Bypass
Not in 1K/2K
Basic 1149.1 boundary scan
Yes
Yes
Yes
Version control
USERCODE INTEST IDCODE HIGHZ
Yes
No
No
No
In-system debug
Yes
No
No
No
Device type ID
Yes
Yes
No
Yes
Tristate pins during test
Yes
No
No
Yes
Notes JTAG boundary-scan is NOT available in
the 7032S, 7064S, and 7096S.
XC9500 Benefits
  • Built-in version control for pattern tracking
  • Efficient system debugging / diagnosis

21
XC9500 Most Flexible Architecture
Altera Max7KS
Lattice 1K/2K/3K
AMD Mach5
Xilinx XC9500
Individual set, reset, clock pterms Individual OE
pterm for each pin 3.3v/5v I/O Number of global
clocks True / complement global clocks Global
set/reset User programmable grounds Maximum
pterms per macrocell
Yes Yes Yes 3 Yes Yes Yes 90
Yes No Yes 2 Yes Reset No 32
No No No 3 1K Only Reset No 20
No No Yes 4 Yes No No 32
Notes 7032S is the exception and does NOT
provide 3.3v/5v I/O capability.
Leading-Edge Architecture Benefits
  • Superior pin-locking architecture
  • Enhanced logic capability
  • Efficient logic implementation

22
Product Comparison
Altera Max7KS
Lattice 1K/2K/3K
AMD Mach5
Xilinx 9500
Description Macrocell range Number of
user I/O pins Best tPD Best fMAX 5V
in-system programmable Pin-locking Endurance
(pgm/erase cycles) JTAG boundary-scan Number
of JTAG instructions 3.3V ISP versions
36 - 288 34 - 192 5ns 125MHz Yes Good 10,000 Yes
7 2H98
32 - 256 36 - 164 5ns 179MHz Yes Fair-Poor 100 7
128 only 4 2Q98
32 - 320 34 - 192 5ns 180MHz Yes Poor 10,000 3K
only 3 2000V
128 - 512 68 - 256 7.5ns 125MHz Yes Fair 100 Yes
6 MachLV
Notes JTAG boundary-scan (1149.1) is NOT
available in the Altera 7032S, 7064S, and 7096S.
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