TOPIC : CATS, BILBO

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TOPIC CATS, BILBO
UNIT 5 BIST and BIST Architectures
Module 5.2 Specific BIST Architectures
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Cyclic Analysis Testing System (CATS)
Cyclic analysis testing system BIST architecture
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Contd

• This architecture is for sequential circuits.
• Sequential circuits are non-linear binary
  sequence generators.
• During test mode, the outputs of S drive the
  inputs.
• If number of outputs is larger than number of
  inputs, extra outputs can be combined by using
  XOR gates.
• If outputs are less than the inputs, some outputs
  can drive more inputs.

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Contd

• Different permutations of interconnections of
  outputs to inputs clearly lead to different test
  effectiveness.
• To test the circuit S, the outputs are connected
  to the inputs and the CUT clocked a pre mentioned
  number of times.
• The number of steps increases with the circuit
  size.
• Area overhead for this technique is low and its
  effectiveness is clearly circuit dependent.

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Built-In Logic-Block Observation (BILBO)

• The below figure shows a n-bit BILBO register.

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Contd

• The inverted output Q is connected to the data
  input of the next cell through a NOR and an XOR.
• Different modes of the register depend on the
  control inputs B1, B2.
• B11, B21? operates in normal mode as shown

Normal mode in BILBO when B1B21
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Contd

• When B1B20, it operates as a shift register
  with scan input Si. The data is complemented as
  it enters the scan register.

Shift register mode in BILBO when B1B20
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Contd

• When B10, B21, all storage cells are reset.
• When B11, B20 it operates as shown in figure
  below

BILBO when B11, B20
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BIST Designs with BILBO

• A given circuit is partitioned to two circuits
• C1, C2.
• To test C1, R1 and R2 are seeded, R1 is put
• into PRPG mode and R2 is put in the
• MISR mode.
• The circuit is run in this mode for defined
• number of clock cycles.

A BIST design with BILBO
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Contd

• The contents of R2 can be scanned out and the
  signature is checked at the end of the test
  process.
• To test C2 R1 is put into MISR mode and R2 is
  put in PRPG mode.
• Thus the entire circuit is tested in two
  sessions.