EECS 270 Introduction to Sequential Logic - PowerPoint PPT Presentation

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EECS 270 Introduction to Sequential Logic

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EECS 270 Introduction to Sequential Logic Prof. Igor L. Markov – PowerPoint PPT presentation

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Title: EECS 270 Introduction to Sequential Logic


1
EECS 270Introduction to Sequential Logic
  • Prof. Igor L. Markov

2
Announcements and Reminders
  • Homeworks are done
  • Regrades are done
  • Labs?
  • Course materials on coursetools
  • Previous lectures
  • Solutions to homeworks practice exams
  • Prof. Markovs office hours _at_EECS 2211
  • Monday 130-2pm Friday 1130-1230pm
  • Prof. Sakallahs OH _at_EECS 2114B

3
Final Exam
  • Sample final posted
  • Solutions on Monday
  • Date December 15 (Thu)
  • 700-900pm
  • Location Dow 1013 and Dow 1006
  • Coverage cumulative
  • All course material since September
  • Closed-book, no calculators/phones/PDAs
  • Two sheets of notes allowed

4
Grading Policies Problem Types
  • No-shows will get INC for the course
  • INC lapsed into E/F will have to retake EECS 270
  • Course grade
  • 30 midterm average, 30 final exam
  • 30 lab grade average, 10 homeworks
  • 10-14 multiple-choice questions
  • 3-4 free-form problems

5
Preparing for the Exam (1)
  • Use slides and textbook(s)
  • Most topics are covered in Wakerly
  • Practice problem-solving!
  • Review past homeworks and exams
  • Sample exam posted

6
Preparing for the Exam (2)
  • Key terminology concepts
  • Mealy vs. Moore, SRAM vs DRAM
  • MUXes vs deMUXes, Latches vs. flip-flops
  • Identify key gates, circuits, theorems
  • Identify core techniques
  • Logic minimization using K-maps
  • Deriving characteristic equations
  • FSM analysis
  • State minimization, etc

7
Preparing for the Exam (3)
  • Identify boilerplate questions
  • Formula equivalence
  • Synthesizing a combinational circuit
  • Synthesizing a sequential circuit
  • Vice versa analysis(what does a given circuit
    do?)
  • Understand how to usestandard components, e.g.,
  • MUXes, decoders, adders/subtractors
  • Latches, J-K FFs, counters, registers

8
Strategies for multiple-choice Qs
  • Identify relevant standard task(s),complete
    them, compare answers
  • Branch-and-bound
  • Perform basic checks
  • Eliminate whats clearly wrong
  • Zoom in on differences
  • Identify incorrect usage
  • Use key identities, theorems
  • Match standard circuit blocks
  • Come up with counter-examples

9
Strategies for Free-Form Problems
  • In what form is the answer expected?
  • Is this a design or analysis problem?
  • Recall related standard tasks, circuits,
    theorems, techniques
  • Look for a transformation, decomposition,logic
    equivalence, etc
  • Extend/reuse standard circuits
  • Solve special/simpler cases,then generalize
  • Assume fewer inputs at first

10
Final Exam QA
  • Some topics within the scope
  • Multi-level optimization dont cares
  • Verilog material from the labs hazards
  • Codes Hamming dist., error-detection, etc
  • Partition refinement memories
  • CMOS (but not layout or manufacturing)
  • Expect a Verilog question
  • There may be a lab question

11
Courses after EECS 270
  • Consider taking
  • Hardware EECS 370, 373, 470, (570)
  • S/W Algos EECS 280, 281, 381
  • CAD EECS 478, (527,578,579)
  • Directed studies EECS 499
  • Research opportunities
  • UROP
  • EECS summer fellowships (?)
  • Check Web pages of professors

12
(No Transcript)
13
Chapter 1
  • Binary signals
  • Number systems
  • Conversion between different bases
  • Arithmetic operations(as algorithms)
  • Gray codes

14
Chapter 2
  • Boolean formulas vs comb. circuits
  • Gates
  • Boolean algebra
  • Basic identities
  • Algebraic manipulation
  • Standard forms
  • Minterms maxterms

15
Chapter 2 (contd)
  • Two-level circuit optimization
  • Two-level circuits
  • K-maps (2-var, 3-var, 4-var)
  • Prime implicants, essential primes
  • POS vs SOP
  • Dont cares
  • Multi-level circuit optimization
  • XOR and other gates

16
Chapter 3
  • Combinational logic design
  • Design concepts (reuse, etc)
  • Design hierarchy, top-down design
  • Verilog (no VHDL)
  • Design objectives and trade-offs
  • PLAs and read-only memory
  • Not covered
  • Technology mapping, cell libraries
  • Verification and simulation

17
Chapter 4
  • Combinational blocks
  • Enabling, selection
  • Decoders/encoders and their circuits
  • Implementing functions with decoders
  • Priority encoders
  • Multiplexers and demultiplexers
  • Circuit implementations
  • Implementing functions with muxes
  • No LUTs

18
Chapter 5
  • Arithmetic circuits
  • Adders (HA, FA)
  • Ripple carry
  • Negative numbers and subtraction
  • Overflow
  • Special cases
  • Incrementing and decrementing
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