The%20Single-Cycle%20Datapath%20and%20Control%20Unit

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ECE 445 Computer Organization

• The Single-Cycle Datapath and Control Unit
• (Lecture 10)

The slides included herein were taken from the
materials accompanying Computer Organization and
Design, 4th Edition, by Patterson and Hennessey,
and were used with permission from Morgan
Kaufmann Publishers.
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Material to be covered ...

• Chapter 4 Sections 1 4
• Appendix D Sections 1 3, 5

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Introduction
4.1 Introduction

• CPU performance factors
• Instruction count
• Determined by ISA and compiler
• CPI and Cycle time
• Determined by CPU hardware
• We will examine two MIPS implementations
• A simplified version - single-cycle
• A more realistic version - pipelined
• Simple subset, shows most aspects
• Memory reference lw, sw
• Arithmetic/logical add, sub, and, or, slt
• Control transfer beq, j

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Instruction Execution

• PC ? instruction memory, fetch instruction
• ALL instructions must be fetched
• Register numbers ? register file, read registers
• ALL instructions must be decoded
• Depending on instruction class
• Use ALU to calculate
• Arithmetic result
• Memory address for load/store
• Branch target address
• Access data memory for load/store
• PC ? target address or PC 4

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CPU Overview (Datapath)
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Multiplexers
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CPU Overview (Control)
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Logic Design Basics

• Information encoded in binary
• Low voltage 0, High voltage 1
• One wire per bit
• Multi-bit data encoded on multi-wire buses
• Combinational element
• Operate on data
• Output is a function of input
• State (sequential) elements
• Store information

4.2 Logic Design Conventions
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Combinational Elements
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Sequential Elements

• Register stores data in a circuit
• Uses a clock signal to determine when to update
  the stored value
• Edge-triggered update when Clk changes from 0 to
  1

What if the D Flip-Flop must retain its current
value (rather than store a new one)?
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Sequential Elements

• Register with write control
• Only updates on clock edge when write control
  input is 1
• Used when stored value is required later

How is the Write (enable) signal implemented?
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Clocking Methodology

• Combinational logic transforms data during clock
  cycles
• Between clock edges
• Input from state elements, output to state
  element
• Longest delay determines clock period

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Building a Datapath

• Datapath
• Elements that process data and addressesin the
  CPU
• Registers, ALUs, muxs, memories,
• Control Unit
• Controls the behavior of the elements that
  comprise the datapath
• We will build a MIPS datapath incrementally
• Refining the overview design

4.3 Building a Datapath
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Instruction Fetch
Stored Program Computer
Program Counter (aka. Instruction Address
Register)
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R-Format Instructions

• Some examples
• add s0, t1, t0
• sub s3, s1, t1
• and t2, t3, s1
• or t5, s6, s7
• sll t1, t0, 3

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R-Format Instructions

• Read two register operands (rs and rt)
• Perform arithmetic/logical operation
• Write register result (rd)

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Load/Store Instructions

• These are I-Format instructions
• Some examples
• lw s0, 32 (t1)
• sw s1, 40 (t2)

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Load/Store Instructions

• Read register operands
• Calculate address using 16-bit offset
• Use ALU, but sign-extend offset
• Load Read memory and update register
• Store Write register value to memory

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Branch Instructions

• These are I-Format instructions
• Some examples
• beq s2, t3, L1
• bne t3, t4, Else

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Branch Instructions

• Read register operands
• Compare operands
• Use ALU
• Subtract and check Zero output
• Calculate target address
• Sign-extend displacement
• Shift left 2 bits (word displacement)
• Add to PC 4
• Already calculated by instruction fetch

What does the Zero output indicate?
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Branch Instructions
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Composing the Elements

• Simple datapath does an instruction in one clock
  cycle
• Each datapath element can only do one function at
  a time
• Hence, we need separate instruction and data
  memories
• Read instruction memory (every instruction must
  be fetched)
• Read or Write data memory (for lw and sw,
  respectively)
• Use multiplexers where alternate data sources are
  used for different instructions

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R-Type/Load/Store Datapath
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R-Type Instructions
rs
25..21
rt
20..16
31..0
15..11
rd
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Example add s0, t0, t1
add
t0
t0
t1
t1
s0
t0 t1
t0 t1
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Example sub s3, s2, s1
sub
s2
s2
s1
s1
s2
s2 - s1
s2 - s1
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Example and t0, s1, s2
and
s1
s1
s2
s2
t0
s1 s2
s1 s2
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Example or s5, t3, s3
or
t3
t3
s3
s3
s5
t3 s3
t3 s3
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Example sll s3, t1, 2
sll
t1
s3
Can the shift operations be implemented with this
datapath?
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R-Type/Load/Store Datapath
Which datapath components are not required for
R-type instructions?
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Questions?