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Revision Mid 2
CS147 Lecture 15

• Prof. Sin-Min Lee
• Department of Computer Science

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Example Determine the product term for the K-Map
below and write the resulting minimum SOP
expression
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Example Use a K-Map to minimize the following
standard SOP expression
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Example Use a K-Map to minimize the following
standard SOP expression
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Mapping Directly from a Truth Table
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Dont Care (X) Conditions

• A situation arises in which input variable
  combinations are not allowed
• Dont care terms either a 1 or a 0 may be
  assigned to the output

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Dont Care (X) Conditions
Example of the use of dont care conditions to
simplify an expression
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Exercise Use K-Map to find the minimum SOP from
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2
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JK Flip-flop

• The most versatile of the flip-flops
• Has two data inputs (J and K)
• Do not have an undefined state like SR flip-flops
• When J K both equal 1 the output toggles on the
  active clock edge
• Most JK flip-flops based on the edge-triggered
  principle

ve edge triggered JK flip-flop

• The C column indicates ve edge triggering
  (usually omitted)

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Timing diagram for JK Flip-flop
Negative Edge Triggered
clock J K Q
toggle JK1
hold JK0
reset J 0 K1
set J 1 K0
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JK from D Flip-flop
J
Q
D
K
CLK
C
Q
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Implementing with a D AND a T flip-flop
Using this FSM with three states, an operating
only on inputs and transitions from one state to
another, we will be using both D and T flip-flops.
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Implementing with a D AND a T flip-flop
Since we have no state 11, our Q(t1) is don't
care XX for both of these transitions.
Consider the first column of the Q(t1) values
to be D and the second to be T and then we
derive two corresponding charts.
D
T
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Implementing with a D AND a T flip-flop
Then we need to derive the corresponding
equations.
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Implementing with a D AND a T flip-flop
We assume that Q(t) is actually a pair of QDQT.
Now, with these equations, we can graph the
results.
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Implementing with a D AND a T flip-flop
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1/1
0/-
01
00
0/0
X/Y X input Youtput
A
B
1/-
1/1
0/-
C
X dont care
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X Q1 Q0 Q1 Q0 Y
0 0 0 0 1 X
0 0 1 0 1 0
0 1 0 0 0 X
0 1 1 X X X
1 0 0 1 0 X
1 0 1 1 0 1
1 1 0 X X X
1 1 1 X X X
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T
X\Q0Q1 00 01 11 10
0 0 0 X 0
1 1 1 X X
X\Q0Q1 00 01 11 10
0 0 0 X 1
1 1 1 X X
T X Q1
JK
X\Q0Q1 00 01 11 10
0 1 1 X 0
1 0 0 X X
X\Q0Q1 00 01 11 10
0 1 1 X 0
1 0 0 X X
X\Q0Q1 00 01 11 10
0 1 1 X 0
1 0 0 X X
J XQ
K X
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Using T Flip Flop and JK Flip Flop

• log24 2, so 2 flip flops are needed to
  implement this FSA

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Step 1 - Translate diagram into StateTable

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Step 2 - Create maps for T and JK

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Step 3 - Determine T, J, and K equations

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Step 4 - Draw resulting diagram

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Figure 9--15 Timing diagram for the counter
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Figure 9--68 State diagram showing the 2-bit
Gray code sequence.
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Figure 9--69 Sequential logic.
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Memory Technology

• Static RAM (SRAM)
• 0.5ns 2.5ns, 2000 5000 per GB
• Dynamic RAM (DRAM)
• 50ns 70ns, 20 75 per GB
• Magnetic disk
• 5ms 20ms, 0.20 2 per GB
• Ideal memory
• Access time of SRAM
• Capacity and cost/GB of disk

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Principle of Locality

• Programs access a small proportion of their
  address space at any time
• Temporal locality
• Items accessed recently are likely to be accessed
  again soon
• e.g., instructions in a loop, induction variables
• Spatial locality
• Items near those accessed recently are likely to
  be accessed soon
• E.g., sequential instruction access, array data

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Taking Advantage of Locality

• Memory hierarchy
• Store everything on disk
• Copy recently accessed (and nearby) items from
  disk to smaller DRAM memory
• Main memory
• Copy more recently accessed (and nearby) items
  from DRAM to smaller SRAM memory
• Cache memory attached to CPU

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Memory Hierarchy Levels

• Block (aka line) unit of copying
• May be multiple words
• If accessed data is present in upper level
• Hit access satisfied by upper level
• Hit ratio hits/accesses
• If accessed data is absent
• Miss block copied from lower level
• Time taken miss penalty
• Miss ratio misses/accesses 1 hit ratio
• Then accessed data supplied from upper level

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Cache Memory

• Cache memory
• The level of the memory hierarchy closest to the
  CPU
• Given accesses X1, , Xn1, Xn

• How do we know if the data is present?
• Where do we look?

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The Cache Hit Ratio

• How often is a word found in the cache?
• Suppose a word is accessed k times in a short
  interval
• 1 reference to main memory
• (k-1) references to the cache
• The cache hit ratio h is then

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Reasons why we use cache

• Cache memory is made of STATIC RAM a
  transistor based RAM that has very low access
  times (fast)
• STATIC RAM is however, very bulky and very
  expensive
• Main Memory is made of DYNAMIC RAM a capacitor
  based RAM that has very high access times because
  it has to be constantly refreshed (slow)
• DYNAMIC RAM is much smaller and cheaper

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Performance (Speed)

• Access time
• Time between presenting the address and getting
  the valid data (memory or other storage)
• Memory cycle time
• Some time may be required for the memory to
  recover before next access
• cycle time access recovery
• Transfer rate
• rate at which data can be moved
• for random access memory 1 / cycle time

(cycle time)-1
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Figure 9--70
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Figure 9--71
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