Lecture 26: Interconnect Modeling, continued

1
Lecture 26 Interconnect Modeling, continued

• EECS 312
• Reading 8.2.2, 8.3.4 (text)
• HW 8 is due now!

2
Last Time

• Wire resistivity gets worse as wires get smaller
  (reverse scaling, different than device delay)
• Power distribution becomes more difficult due to
  IR drops and higher current densities
• Lumped wire delay overestimates actual delay
  (distributed)
• Because the entire capacitance is NOT charged
  through the full wire resistance
• Wire RC delay increases quadratically with line
  length as both R and C rise linearly
• This has implications on how to reduce RC delay

3
Lecture Overview

• Combating RC delay
• Repeaters
• Noise due to wires
• Capacitive crosstalk voltage glitches and
  increasing delay

4
Delay expressions, revisit
Assumes step input Vin
We will typically have a load capacitance CL at
node Vout
5
How to reduce RC delay

• Since RC delay is quadratic with length, reducing
  length is key
• Note 22 4 and 11 2 but 12 12 2

driver
receiver
driver
receiver
L 2 units
6
Repeaters
Repeater
A repeater is a strong driver (usually an
inverter or pair of inverters for non-inversion)
that is placed along a long RC line to break up
the line and reduce delay We need to determine
the optimal number of repeaters and their size
based on wire and device delay properties
7
Repeater Derivation
Eq. 8.34 of text
8
Repeaters Impact
Repeaters are simply large inverters inserted
along a global interconnect to reduce the RC delay
9
Repeaters vs. Cascaded Buffers

• Repeaters are used to drive long RC lines
• Breaking up the quadratic dependence of delay on
  line length is the goal
• Typically sized identically
• Cascaded buffers are used to drive large
  capacitive loads, where there is no parasitic
  resistance
• We put all buffers at the beginning of the load
• This would be pointless for a long RC wire since
  the wire RC delay would be unaffected and would
  dominate the total delay

10
Capacitive Crosstalk Noise
Due to interwire capacitance, neighboring wires
can interact with each other This is referred to
as crosstalk noise
11
Cross-sectional view
A quiet victim wire is imposed upon by one or
more adjacent aggressor wires that are switching
rapidly Charge injected across Cc results in a
temporary (in static logic) glitch in voltage
from the supply rail at the victim Dynamic logic
is more susceptible since its non-restoring
12
Noise Pulses can be large
Impact forward-bias drain-substrate p-n
junctions, enhance device stress, falsely switch
state of fan-out
13
Simple Noise Model (Rubio)
Model assumptions no wire resistance considered,
Tr is rise time of aggressor signal, Rv is the
effective driver resistance of the victim, Cv is
the ground capacitance of the victim
where
VddRvCc/Tr is the maximum possible noise ?
given by VIRRvCcdV/dt Last term relates to
how easily the charge at the victim net can be
removed through Rv relative to the transition
time of aggressor
14
Linear Resistance Assumption
Slope here is fairly constant with VgsVdd
(operating point for NMOS holding output to
GND) Inverse of this slope Reff Replace the
victim driver by a linear resistor Only problem
if noise gets too big, the approximation becomes
worse (R grows)
15
How to Battle Capacitive Crosstalk
Unrealistic need tight packing to reduce chip
area, cost
16
Delay Degradation
- Impact of neighboring signal activity on
switching delay - When neighboring lines switch
in opposite direction of victim line, delay
increases
Cc
Miller Effect - Both terminals of capacitor are
switched in opposite directions (0 ? Vdd, Vdd
? 0) - Effective voltage is doubled and
additional charge is needed (from QCV) just
like overlap capacitances in devices
17
Lecture Summary

• Repeaters are inserted along long global wires to
  reduce the intrinsic wire RC delay
• Common practice in mid-high performance designs
  today
• Crosstalk noise refers to injected charge across
  interwire (coupling) capacitance
• A quiet wire can experience a voltage glitch as a
  result, leading to functional failure or worsened
  reliability
• This can also increase delay, when adjacent lines
  switch at the same time in opposite directions