CPRE 583: Reconfigurable Computing Systems, Fall 2004

1
CPRE 583 Reconfigurable Computing Systems, Fall
2004

• Instructor
• Akhilesh Tyagi
• Tel [phone]
• Email tyagi_at_iastate.edu
• Office Hours Tu1000-1100 F 200-300
• Web Page http//class.ee.iastate.edu/tyagi/cpre58
  3/cpre583.html or Follow link from home page of
  the department
• Text Book Only references and paper
• Grading
• Homework Once every 10 days 40 of grade
• Notes Scribing You are responsible for one-two
  lectures, 10 of grade
• Research paper presentation 10 of grade
• Project 40 of grade

2
Outline of the Course

• Introduction to Adaptive/Reconfigurable Computing
  
• FPGA Technology and Architectures
• Spatial Computing Architectures
• Adaptive Network Architectures
• Reconfigurable Computing Architectures
• Specialized computing

3
Introduction

• Rapidly changing field
• vacuum tube -gt transistor -gt IC -gt VLSI
• memory capacity and processor speed is doubling
  every 1.5 years
• So why we need reconfigurable computing?
• Well, we always had it
• Todays computer are one of the forms of
  reconfigurable computers
• Each user sees it mostly fit to do their
  computation
• Specialized processors can not keep up with
  technology due to volume (mass production) of
  commercial processors
• However, cheap reconfigurable computing can still
  compete with commercial processor in
  cost/performance ratio
• FPGA make such implementations feasible

4
General Purpose Computing

• Reconfiguration/Customization can occur at many
  levels
• Market level
• Market for device
• System level
• Running different pieces of code at different
  times
• Application level
• Same resources used by different instructions
  rather than building various different functional
  units
• Algorithm level
• Different algorithms can be used to realize the
  same application

5
Consider Reconfiguration

• Here is a function AX2 BX C
• It can be viewed as steps of many binary
  operations
• XX, BX, A(XX), (BX)C, (A(XX)) ((BX)C)
• Takes three time steps using three mult and two
  add FU
• AX, (AX)B, (AXB)X, ((AXB)X)C
• Takes four time steps using two mult and two add
  FU
• AXB, (AXB)XC
• Takes two multiply-add time steps using one
  mult-add FU and two muxes
• But what if we have a unit that can be configured
  as mult or add
• mux (X, B, C), mux (A, res) and reconfigurable
  unit

6
Design a system

• We may like to design systems with flexibility
• We also like to minimize amount of hardware
• 3 bit input, 24 bit output (like a controller for
  RISC processor)
• 4 bit input, one of any of 64K functions
• 12 bit input, 16 bit output, but only 16 unique
  combinations