PKUnity: A SoC Design and Verification Platform

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PKUnity A SoC Design and Verification Platform

• Lu Junlin
• MicroProcessor RD Center (MPRC)
• Peking University

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Outline

• PKUnity SoC Platform Features
• Multi-Layers Verification Framework
• CDC Verification Tool
• Future Works

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Outline

• PKUnity SoC Platform Features
• Multi-Layers Verification Framework
• CDC Verification Tool
• Future Works

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What for

• Providing a PLATFORM for implementing and
  verifying NEW IDEALS in Nanotechnologies

Low Power
Behavioral Level Simulation (SystemC)
Softwares
Compiler
Synthesis
RTL Simulation/Emulation (Verilog/VHDL)
New Ideas
CPU
FPGA Prototyping
Silicon Proving
Network
On-chip communication
PKUnity Platform
Multi-Media Processing
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What is

• PKUnity Platform includes
• a scalable and configurable SoC architecture
• a series of UniCore CPU
• plenty of communication IPs
• a verification framework
• some verification tools
• compilation tool chain and OS based on UniCore

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PKUnity Architecture
Low Speed I/O and System Modules
UniCore CPU
Memory and High Speed I/O
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Design Features
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Design Features

• CPU
• 600MHz UniCore
• 8-Stage Pipeline
• 64-bit Floating Point Co-Processor
• 16KB I/D Cache
• 2-Port Bus Interface

• Main Memory
• DDR (Double Data Rate) SDRAM
• 166MHz Clock and 64-bit Width
• 2 Memory Access Channels

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Design Features

• High Speed I/O Devices
• 10M/100M/1G Ethernet MAC
• 66MHz PCI Bridge
• IDE SATA Controller
• USB OTG Controller

• Low Speed I/O Devices
• UART
• I2C
• SPI
• AC97
• PS/2

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Design Flow
Design and Implementation
RTL Simulation and Emulation
SystemC-based HW/SW Co-verification
FPGA Prototyping
RTL Sign Off
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Challenges

• Gap between CPU and Main Memory
• Different Bus Bandwidth Requirements
• Power Supply

Design

Verification

• Complex Communication Protocol
• Lots of Asynchronous Clock Domains

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Design Solutions

• Two-Layer bus
• CPU-MEM bus
• IO-MEM bus

Fast Clock Best Performance
CPU-MEM Bus
Minimize CPU-MEM bandwidth gap
Reduce the power supply
Slow Clock Enough Performance
IO-MEM Bus
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Verification Solutions

• Multi-Layer Verification Framework
• For Complex Communication Protocol

• CDC Verification Tool
• For Lots of Asynchronous Clock Domains

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Outline

• PKUnity SoC Platform Features
• Multi-Layers Verification Framework
• CDC Verification Tool
• Future Works

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Verification Challenges

• Complex Communication Protocol
• AHB vs. DDR SDRAM
• AHB vs. PCI
• AHB vs. MAC
• AHB vs. USB OTG
• AHB vs. IDE
• APB vs. AC97

Its hard to cover all the transaction types!
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Verification Methodology

• Multi-Layer
• Signal Layer
• Bus Layer
• Transaction Layer
• Scenario Layer

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Self Checking

• Self Checking by two channels

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Verification Framework
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Example

• Ethernet MAC Verification Coverage

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Outline

• PKUnity SoC Platform Features
• Multi-Layers Verification Framework
• CDC Verification Tool
• Future Works

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Whats CDC

• CDC Clock Domain Crossing

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Challenges

• Lots of Asynchronous Clock Domains
• The relationship of clocks is static in the
  normal simulation
• Its difficult to find setup time and hold time
  violation (metastable state)

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Method (Step 1)

• 1. Find all the CDC paths
• Handshake Logic
• Gray code counter
• ...

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Method (Step 2)
2. Insert a module which can provide random
delays on each CDC paths
CDC_delay U_RdDMA_D (.in(RdDMAH),
.out(RdDMAH_d)) CDC_delay U_WrDMA_D
(.in(WrDMAH), .out(WrDMAH_d)) Clk_jitter
U_ICLK(.in(ICLK), .out(ICLK_j)) CDC_monitor
U_RdDMA_M (.in(RdDMAH_d)) CDC_monitor U_WrDMA_M
(.in(WrDMAH_d)) always _at_ (posedge HCLK) begin
RdDMAH lt (RWCON !RdDMAH) WrDMAH lt (!RWCON
!WrDMAH) end assign XCS lt !WrDMAH_d
!RdDMAH_d CS0 always _at_ (posedge ICLK_j) NCS
lt (WrReqI RdReqI) XCS
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Method (Step 3)
3. Add reasonable delays on the CDC paths in
simulation repeatedly
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Example

• A commercial ATA-5 IDE controller IP
• The table shows coverage comparability after 30
  transactions finished
• The right diagram show the full coverage growth

Table 1 Comparing Code Coverage with CDC Coverage. Table 1 Comparing Code Coverage with CDC Coverage. Table 1 Comparing Code Coverage with CDC Coverage. Table 1 Comparing Code Coverage with CDC Coverage. Table 1 Comparing Code Coverage with CDC Coverage. Table 1 Comparing Code Coverage with CDC Coverage.
Module Name Function Description Num.of Lines LineCoverage Num. of CDCcoverage points CDCCoverage
m3s010fa Asynchronous FIFO 426 97.14 14336 0.40
m3s008fa Asynchronous FIFO Control 917 95.14 5170 0.39
m3s007fa IDE PIO/DMA Timing Control 353 100 1458 0.27
m3s012fa IDE UDMA Timing Control 470 100 972 0.41
m3s005fa AMBA AHB DMA Control 471 95.70 620 2.26
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Outline

• PKUnity SoC Platform Features
• Multi-Layers Verification Framework
• CDC Verification Tool
• Future Works

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Future Works

• Communication Architecture
• Bandwidth Allocation Algorithm
• CDC Coverage Improvement

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Thank You!