IP%20for%20Xilinx

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IP for Xilinx
Academy Training Core Solutions http//www.xilin
x.com/products/logicore/logicore.htm Products htt
p//www.xilinx.com/products/logicore/tblcores.htm
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High-density FPGA design
Example system on an FPGA

• Cores are mainstream for 70K gate ASICs
• Million gate FPGAs are here
• Requires new design methods
• Cores essential to maintain time-to-market value
  of FPGAs
• reduce design risk
• reduce compile time

Bus Interfaces
Custom Design
Memory Interfaces
App Specific Modules
Processor Interfaces
DMA Modules
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Complete Core SolutionsReduce Time to Market
Design From Scratch
Reference Design, Generic Core
Complete FPGA Core Solution
Pre-verified Designs
Area Timing Optimized
Complete Flexible Design
Little Knowledge of Function Required
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Cot of Core Development

• Assumptions
• Sr. design engineer (20K/mo burdened cost)
• Design rate 5 CLBs/day
• Functional timing simulation
• Placed, routed, hardware tested
• Cost Analysis
• 250 CLBs(1day/5CLBs)(1mo/21days) 2.4 mo
• 2.4mo20K/mo 48,000

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Xilinx CORE Solutions Products
A core sold, distributed and supported by
Xilinx. Core enabling technologies designed to
ease both the develop- ment and the use of
FPGA-based cores (i.e. CORE Generator)
A core sold, distributed and supported by a
Xilinx AllianceCORE partner. The core has gone
through Xilinx productization process before
promotion by Xilinx.
Xilinx Program for Engineering Resources from
Third Parties - Certified consultants to aid in
design and IP integration.
Reference Designs
Untested design example and application note
available from Xilinx, unsupported and free of
charge.
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Important CORE Solutions Contacts

• LogiCORE Products
• Marketing Per Holmberg, per.holmberg_at_xilinx.com
  408-879-5318
• PCI Applications Jim McManus, jim.mcmanus_at_xilinx.
  com 408-879-4729
• DSP Applications Sabine Lam, sabine.lam_at_xilinx.co
  m 408-879-5095
• Vertical Markets
• Marketing Paul Laity, paul.laity_at_xilinx.com
  408-879-4548
• AllianceCORE Products
• Marketing Mark Bowlby, mark.bowlby_at_xilinx.com
  408-879-5381
• Applications Anil T.L.N., anil.telikepalli_at_xilinx
  .com 408-879-6955
• XPERTS Program
• Marketing Umesh Bhat, umesh.bhat_at_xilinx.com
  408-879-4592

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Partnerships for CompleteProgrammable Logic
Solutions
Program Info http//www.xilinx.com/products/logic
ore/alliance/tblpart.htm
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An AllianceCORE uccess!Reed Solomon

• Customer Wavtrace
• Existing Altera user - not Xilinx
• Looking at LSI Logic for Reed Solomon Core
• Altera and Xilinx both offered ISS core
• Under pricing pressure, Altera offered own core
• The Result - Xilinx and ISS Win!
• Communication was key
• Complete solution HardWire ISS cores
• 8 software seats 20 sockets
• 4 month process
• What Can We Learn?
• Win the core, win the war
• ISS solution better than LSIs

PARTNER
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Partners
As of November, 1998
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Core Productization Process

• Core Selection
• The right cores for programmable logic
• Benefit A practical programmable logic core
• Core Qualification
• Available in a Xilinx-optimized format with
  constraints
• Xilinx Flow Checks netlist version to verify
  density/performance (not source code)
• Xilinx DOES NOT verify internal functionality
• Benefit Low risk
• Core Integration
• Support tools (i.e. hardware/software)
• Documentation and application support
• Benefits Fast integration, time-to-market

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AllianceCORE Product StagesTo ensure
high-quality 3rd-party cores
Stage 1
Stage 2
Stage 3
Released AllianceCORE Products
IP1
Productization Process
IP5
IP1
IP2
IP3
IP1
IP2
IP3
IP1
IP2
IP3
Products and Expertise
IP4
IP5
IP6
IP4
IP5
IP6
IP4
IP5
IP6
AllianceCORE Partner
AllianceCORE Partner
Company Status
3rd Party
Apply
Accepted
Producing
Activity Status
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Basics of Using the Program

• Core Partnerships are Relatively New
• Its natural to have questions
• The Time to Start is Now
• We sell time-to-market
• Big devices need (many) cores
• Cannot continue to, without 3rd-party cores
• Customers are interested
• We Learn to use this Together
• Field, factory and partners

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First Sales ScenarioYou and customer identify a
need

• 1. Download Data Sheet from WebLINX
• www.xilinx.com/products/logicore/tblpart.htm
• Call factory if needed
• 2. Contact Partner
• Identify yourself as Xilinx representative
• Describe opportunity
• Decide if there is a fit
• 3. Set up a Conference Call
• 4. Stay Involved and Communicate

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Second Sales ScenarioCustomer has already
contacted partner

• Insert Yourself into the Process
• Find out the status
• Introduce Yourself to Partner
• Begin and maintain communication
• Stay Involved and Communicate

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Lead Registration GuidelinesRules for Partners
and Xilinx

• Whoever Brings Lead First (Xilinx or Partner),
  Owns It
• First requested vendor is co-owner
• Only offer requested solution(s)
• Get other party(s) involved
• Tell if customer later asks for competing
  solution
• Open game if original request not vendor-specific
• Cooperate and Communicate
• Help us learn as we go

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Acquiring AllianceCORE Products

• Purchase made directly with Partner
• Xilinx Netlist version lt Source Code
• Netlist restricted for use in Xilinx
• Always ask which version the partner is quoting
• Partner guarantees functionality
• Licensing varies
• Single use
• Multi-use site license

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Recommendations

• Analyze the needs of your customer base
• Find partners with expertise in those areas
• Get to know two or three proactively
• Call or visit them
• Which one are in your area?
• Start a relationship
• 25 partners is too many

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Virtex Status

• Many Partners are trained on Virtex
• Partner-specific training occurred December 1998
• Ongoing training of others
• Virtex is becoming a de-facto IP platform
• All NEW partner core development is on Virtex
• Always ASK partner about Virtex availability of a
  core
• Current 4K cores being converted

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Released Products

• Bus Interfaces
• CAN
• FireWire (IEEE 1394)
• I2C (2 types)
• PCMCIA (2 types)
• USB (3 types)
• Communications
• ATM Cell Assembler
• ATM Cell Delineation
• 10/100 Ethernet MAC
• CRC (10- 32-bit)
• DES Engine (2 partners)
• HDLC (2 types)
• Reed Solomon (2 partners)
• T1 Framer
• UTOPIA (master slave)
• Viterbi Decoder

Image Processing YUV to RGB Processor
Peripherals UARTs (7 types) 2901 2910A 8237 8251 8
254 8255 (3 partners) 8256 8259 (2
partners) 8279 9128 DRAM Controller SDRAM
Controller RISC Processors (2 types) Demo Boards
Software (15)
As of February 1999
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AllianceCORE Guidelines

• Check WebLINX FIRST for core availability
• Xilinx flow checks netlist, not source code
• Partner guarantees functionality
• Work with partner
• Honor leads owned by the partner
• Know if partner is quoting source code or netlist
• Get to know a few of them