Gate-Length Biasing A Highly Manufacturable Approach To Leakage Control

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Gate-Length BiasingA Highly Manufacturable
Approach To Leakage Control
Methodology Details
Results Leakage

• Leakage power reduction
• Single Vt designs 14-26
• Dual Vt designs 4-15

• Granularity Freedom to assign different biased
  gate-lengths to different devices. We consider
  three options
• Technology level All devices in the library have
  the same biased gate-length.
• Cell level All devices in a cell have the same
  biased gate-length. Devices in different cells
  may have different biased gate-lengths.
• Device level All devices are free to have an
  independent biased gate-length.
• Our approach For each cell, NMOS devices have
  one biased gate-length and PMOS devices have an
  independent biased gate-length. Devices In
  different cells have independent biased
  gate-lengths.
• Leakage optimizer Simple TILOS like sizer
  starts with all fastest cells, replaces cells
  that have slack with slower, low-leakage variants.

Spice Netlists
Spice Model
Biased Gate-Length
Granularity
Characterize and augment standard cell library
such that each master has a biased gate-length
variant
Extended Standard Cell Library
Circuit Netlist
Dynamic Leakage Power Estimate
Leakage Optimizer Uses slower, low-leakage cells
in non-critical paths Uses faster, high-leakage
cells in critical paths
Modified Netlist
Circuit delay penalty of less than 2.5
Results Manufacturability
High correlation between drawn and printed
gate-length
Printed and drawn gate-lengths of devices in
AND2X6. Unbiased gate-length is 130nm biased
gate-length is 136nm. Tools Mentor Calibre for
OPC Printimage for litho simulation
Device Numer Gate Length (nm) Gate Length (nm) Gate Length (nm) Gate Length (nm) Gate Length (nm) Gate Length (nm)
Device Numer PMOS PMOS PMOS NMOS NMOS NMOS
Device Numer Unbiased Biased Diff. Unbiased Biased Diff.
1 125 132 7 126 132 6
2 124 126 2 126 129 3
3 124 126 2 126 129 3
4 121 127 6 124 130 6
5 121 127 6 122 128 6
6 122 128 6 122 128 6
7 125 131 6 122 131 7
Process window improves with gate-length
DOF(µm) ELAT() for 130nm ELAT() for 136nm
0.09 7.66 7.71
0.33 6.97 7.04
0.50 5.98 6.23
0.67 4.67 5.02
1.00 2.06 2.71
CD tolerance 13nm ELAT Exposure latitude DOF
Depth of Focus Tools KLA-Tencor Prolith
Results generated by 2000 Monte-Carlo
simulations ?WID ?DTD3.33nm. Variations assumed
to be Gaussian with no correlation.