EEM 486: Computer Architecture Lecture 3 Designing Single Cycle Control

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EEM 486 Computer ArchitectureLecture
3Designing Single Cycle Control
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The Big Picture Where are We Now?
3
An Abstract View of the Implementation
Control
Ideal Instruction Memory
Control Signals
Conditions
Instruction
Rd
Rs
Rt
5
5
5
Instruction Address
A
Data Address
Data Out
32
Rw
Ra
Rb
32
Ideal Data Memory
32
32 32-bit Registers
Data In
Next Address
B
Clk
Clk
32
Datapath
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Recap A Single Cycle Datapath

• We have everything except control signals
  (underline)

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Recap Meaning of the Control Signals

• nPC_MUX_sel 0 ? PC lt PC 4 1 ? PC lt PC
  4 SignExt(Im16) 00

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Recap Meaning of the Control Signals

• MemWr 1 ? write memory
• MemtoReg 0 ? ALU 1 ? Mem
• RegDst 0 ? rt 1 ? rd
• RegWr 1 ? write register

• ExtOp zero, sign
• ALUsrc 0 ? regB 1 ? immed
• ALUctr add, sub, or

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RTL The Add Instruction

• add rd, rs, rt
• memPC Fetch the instruction from
  memory
• Rrd lt- Rrs Rrt The actual operation
• PC lt- PC 4 Calculate the next
  instructions address

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Instruction Fetch Unit at the Beginning of Add

• Fetch the instruction from Instruction memory
• Instruction lt- memPC
• Same for all instructions

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The Single Cycle Datapath During Add

• Rrd lt- Rrs Rrt

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Instruction Fetch Unit at the End of Add

• PC lt- PC 4
• This is the same for all instructions except
  Branch and Jump

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The Single Cycle Datapath During Or Immediate

• Rrt lt- Rrs or ZeroExtImm16

RegDst
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The Single Cycle Datapath During Or Immediate
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The Single Cycle Datapath During Load

• Rrt lt- Data Memory Rrs SignExtimm16

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The Single Cycle Datapath During Store

• Data Memory Rrs SignExtimm16 lt- Rrt

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The Single Cycle Datapath During Store
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The Single Cycle Datapath During Branch

• if (Rrs - Rrt 0) then Zero lt- 1
  else Zero lt- 0

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Instruction Fetch Unit at the End of Branch

• What is encoding of nPC_sel?
• Direct MUX select?
• Branch / not branch

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Step 4 Given Datapath RTL -gt Control
Instructionlt310gt
Inst Memory
lt1115gt
lt2125gt
lt015gt
lt2125gt
lt1620gt
Adr
Op
Fun
Imm16
Rd
Rs
Rt
Control
ALUctr
RegDst
ALUSrc
ExtOp
MemtoReg
MemWr
nPC_sel
RegWr
Zero
DATA PATH
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Summary of Control Signals
inst Register Transfer ADD Rrd lt Rrs
Rrt PC lt PC 4 ALUsrc RegB, ALUctr
add, RegDst rd, RegWr, nPC_sel
4 SUB Rrd lt Rrs Rrt PC lt PC
4 ALUsrc RegB, ALUctr sub, RegDst rd,
RegWr, nPC_sel 4 ORi Rrt lt Rrs
zero_ext(Imm16) PC lt PC 4 ALUsrc Im,
Extop Z, ALUctr or, RegDst rt, RegWr,
nPC_sel 4 LOAD Rrt lt MEM Rrs
sign_ext(Imm16) PC lt PC 4 ALUsrc Im,
Extop Sn, ALUctr add, MemtoReg,
RegDst rt, RegWr, nPC_sel 4 STORE MEM
Rrs sign_ext(Imm16) lt Rrt PC lt PC 4
ALUsrc Im, Extop Sn, ALUctr add, MemWr,
nPC_sel 4 BEQ if ( Rrs Rrt ) then PC
lt PC sign_ext(Imm16) 00 else PC lt PC
4 nPC_sel Br, ALUctr sub
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Summary of the Control Signals
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Concept of Local Decoding
op
00 0000
00 1101
10 0011
10 1011
00 0100
R-type
ori
lw
sw
beq
RegDst
1
0
0
x
x
ALUSrc
0
1
1
1
0
MemtoReg
0
0
1
x
x
RegWrite
1
1
1
0
0
MemWrite
0
0
0
1
0
0
0
0
0
1
Branch
x
1
1
x
0
ExtOp
ALUopltN0gt
R-type
Or
Add
Add
Sub
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Encoding of ALUop

• In this exercise, ALUop has to be 2 bits wide to
  represent
• (1) R-type instructions
• I-type instructions that require the ALU to
  perform
• (2) Or, (3) Add, and (4) Subtract
• To implement the full MIPS ISA, ALUop has to be 3
  bits to represent
• (1) R-type instructions
• I-type instructions that require the ALU to
  perform
• (2) Or, (3) Add, (4) Subtract, (5) And, and (6)
  Xor

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Decoding of the func Field
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Truth Table for ALUctr
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Logic Equation for ALUctrlt2gt

• ALUctrlt2gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt2gt funclt1gt
  !funclt0gt

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Logic Equation for ALUctrlt1gt

• ALUctrlt1gt !ALUoplt2gt !ALUoplt1gt
• !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt2gt !funclt0gt

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Logic Equation for ALUctrlt0gt

• ALUctrlt0gt !ALUoplt2gt ALUoplt1gt
• ALUoplt2gt !funclt3gt funclt2gt
  !funclt1gt funclt0gt
• ALUoplt2gt funclt3gt !funclt2gt
  funclt1gt !funclt0gt

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ALU Control Block

• ALUctrlt2gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt2gt funclt1gt
  !funclt0gt
• ALUctrlt1gt !ALUoplt2gt !ALUoplt1gt
  !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt2gt !funclt0gt
• ALUctrlt0gt !ALUoplt2gt ALUoplt1gt ALUoplt2gt
  !funclt3gt
  funclt2gt !funclt1gt funclt0gt
  ALUoplt2gt funclt3gt
  !funclt2gt funclt1gt !funclt0gt

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Step 5 Logic For Each Control Signal

• nPC_sel lt if (OP BEQ) then Br else 4
• ALUsrc lt if (OP Rtype) then regB else
  immed
• ALUctr lt if (OP Rtype) then
  funct elseif (OP ORi) then
  OR elseif (OP BEQ) then sub else
  add
• ExtOp lt _____________
• MemWr lt _____________
• MemtoReg lt _____________
• RegWr lt_____________
• RegDst lt _____________

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Step 5 Logic for Each Control Signal

• nPC_sel lt if (OP BEQ) then Br else 4
• ALUsrc lt if (OP Rtype) then regB else
  immed
• ALUctr lt if (OP Rtype) then
  funct elseif (OP ORi) then OR
  elseif (OP BEQ) then sub else
  add
• ExtOp lt if (OP ORi) then zero else sign
• MemWr lt (OP Store)
• MemtoReg lt (OP Load)
• RegWr lt if ((OP Store) (OP BEQ)) then
  0 else 1
• RegDst lt if ((OP Load) (OP ORi)) then
  0 else 1

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Truth Table for the Main Control
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Truth Table for RegWrite

• RegWrite R-type ori lw
• !oplt5gt !oplt4gt !oplt3gt !oplt2gt !oplt1gt
  !oplt0gt (R-type)
• !oplt5gt !oplt4gt oplt3gt oplt2gt !oplt1gt
  oplt0gt (ori)
• oplt5gt !oplt4gt !oplt3gt !oplt2gt oplt1gt
  oplt0gt (lw)

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PLA Implementation of the Main Control
.
.
.
.
.
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Putting it All Together A Single Cycle Processor
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Recap An Abstract View of the Critical Path
(Load)
Critical Path (Load Operation) PCs
Clk-to-Q Instruction Memorys Access Time
Register Files Access Time ALU to
Perform a 32-bit Add Data Memory Access
Time Setup Time for Register File Write
Clock Skew
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Worst Case Timing (Load)
Clk
Clk-to-Q
New Value
Old Value
PC
Instruction Memory Access Time
Rs, Rt, Rd, Op, Func
Old Value
New Value
Delay through Control Logic
ALUctr
Old Value
New Value
ExtOp
Old Value
New Value
ALUSrc
Old Value
New Value
MemtoReg
Old Value
New Value
Register Write Occurs
RegWr
Old Value
New Value
Register File Access Time
busA
Old Value
New Value
Delay through Extender Mux
busB
Old Value
New Value
ALU Delay
Address
Old Value
New Value
Data Memory Access Time
busW
Old Value
New
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Drawback of this Single Cycle Processor

• Long cycle time
• Cycle time must be long enough for the load
  instruction
• PCs Clock -to-Q
• Instruction Memory Access Time
• Register File Access Time
• ALU Delay (address calculation)
• Data Memory Access Time
• Register File Setup Time
• Clock Skew
• Cycle time for load is much longer than needed
  for all other instructions

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Summary

• Single cycle datapath gt CPI1, CCT gt long
• 5 steps to design a processor
• 1. Analyze instruction set gt datapath
  requirements
• 2. Select set of datapath components establish
  clock methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
  determine setting of control points that effects
  the register transfer.
• 5. Assemble the control logic
• Control is the hard part
• MIPS makes control easier
• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates